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Header connectors

Two high-density header connectors enable you to fit a LogicTile FPGA board to the daughterboard site on the V2M‑Juno motherboard.

Header X, J1, routes the Thin Links buses between the Juno Arm® Development Platform SoC on the V2M‑Juno motherboard and the FPGA on the LogicTile daughterboard fitted in the daughterboard site.

Header Y, J4, routes the buses and power interconnect between the V2M‑Juno motherboard and the LogicTile FPGA daughterboard.

The constraints file, an415_rapper.xdc, available in Application Note AN415 Example LogicTile Express 20MG design for a V2M-Juno Motherboard, lists the header signals.

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