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This chapter introduces the processor and processor instruction set.
About the processor
The Cortex®‑M3 is a low-power processor that features low gate count, low interrupt latency, and low-cost debug. It is intended for deeply embedded applications that require optimal interrupt response features.
Processor features list
The processor includes a core, a Nested Vectored Interrupt Controller (NVIC), high-performance bus interfaces, and other features.
The processor incorporates three external bus interfaces, an ETM interface that allows the connection of an Embedded Trace Macrocell, an AHB Trace Macrocell interface that enables simple connection of an ETM to the processor, and an Advanced High-performance Bus Access Port (AHB-AP) interface for debug accesses.
Optional implementation components
You can configure your processor implementation to include optional components. For example, a Memory Protection Unit (MPU), Flash Patch and Breakpoint (FPB), and Data Watchpoint and Trace Unit (DWT).
The information supplied with this product includes a Technical Reference Manual, an Integration and Implementation manual, together with design flow, architecture, and protocol information.
This section lists the differences in functionality between product revisions.