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DWT Programmers' model

Table showing the DWT registers. Depending on the implementation of your processor, some of these registers might not be present. Any register that is configured as not present reads as zero.

Table 9-1 DWT register summary

Address Name Type

Reset

Description
0xE0001000 DWT_CTRL RW

Possible reset values are:

  • 0x40000000 if four comparators for watchpoints and triggers are present.
  • 0x4F000000 if four comparators for watchpoints only are present.
  • 0x10000000 if only one comparator is present.
  • 0x1F000000 if one comparator for watchpoints and not triggers is present.
  • 0x00000000 if DWT is not present.

Control Register.

0xE0001004 DWT_CYCCNT RW 0x00000000 Cycle Count Register
0xE0001008 DWT_CPICNT RW - CPI Count Register
0xE000100C DWT_EXCCNT RW - Exception Overhead Count Register
0xE0001010 DWT_SLEEPCNT RW - Sleep Count Register
0xE0001014 DWT_LSUCNT RW - LSU Count Register
0xE0001018 DWT_FOLDCNT RW - Folded-instruction Count Register
0xE000101C DWT_PCSR RO - Program Counter Sample Register
0xE0001020 DWT_COMP0 RW - Comparator Register0
0xE0001024 DWT_MASK0 RW -

Mask Register0.

The maximum mask size is 32KB.

0xE0001028 DWT_FUNCTION0 RW 0x00000000 Function Register0
0xE0001030 DWT_COMP1 RW - Comparator Register1
0xE0001034 DWT_MASK1 RW -

Mask Register1.

The maximum mask size is 32KB.

0xE0001038 DWT_FUNCTION1 RW 0x00000000 Function Register1
0xE0001040 DWT_COMP2 RW - Comparator Register2
0xE0001044 DWT_MASK2 RW -

Mask Register2.

The maximum mask size is 32KB.

0xE0001048 DWT_FUNCTION2 RW 0x00000000 Function Register2
0xE0001050 DWT_COMP3 RW - Comparator Register3
0xE0001054 DWT_MASK3 RW -

Mask Register3.

The maximum mask size is 32KB.

0xE0001058 DWT_FUNCTION3 RW 0x00000000 Function Register3
0xE0001FD0 PID4 RO 0x04 Peripheral identification registers
0xE0001FD4 PID5 RO 0x00
0xE0001FD8 PID6 RO 0x00
0xE0001FDC PID7 RO 0x00
0xE0001FE0 PID0 RO 0x02
0xE0001FE4 PID1 RO 0xB0
0xE0001FE8 PID2 RO 0x3B
0xE0001FEC PID3 RO 0x00
0xE0001FF0 CID0 RO 0x0D Component identification registers
0xE0001FF4 CID1 RO 0xE0
0xE0001FF8 CID2 RO 0x05
0xE0001FFC CID3 RO 0xB1

DWT registers are described in the ARM®v7M Architecture Reference Manual. Peripheral Identification and Component Identification registers are described in the ARM® CoreSight™ Components Technical Reference Manual.

Note

  • Cycle matching functionality is only available in comparator 0.
  • Data matching functionality is only available in comparator 1.
  • Data value is only sampled for accesses that do not produce an MPU or bus fault. The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst.
  • The FUNCTION field in the DWT_FUNCTION1 register is overridden for comparators given by DATAVADDR0 and DATAVADDR1 if DATAVMATCH is also set in DWT_FUNCTION1. The comparators given by DATAVADDR0 and DATAVADDR1 can then only perform address comparator matches for comparator 1 data matches.
  • If the data matching functionality is not included during implementation it is not possible to set DATAVADDR0, DATAVADDR1, or DATAVMATCH in DWT_FUNCTION1. This means that the data matching functionality is not available in the implementation. Test the availability of data matching by writing and reading the DATAVMATCH bit in DWT_FUNCTION1. If this bit cannot be set then data matching is unavailable.
  • ARM does not recommend PC match for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM.
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