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About the TPIU

The Cortex‑M4 TPIU is an optional component that acts as a bridge between the on-chip trace data from the Embedded Trace Macrocell (ETM) and the Instrumentation Trace Macrocell (ITM), with separate IDs, to a data stream. The TPIU encapsulates IDs where required, and the data stream is then captured by a Trace Port Analyzer (TPA).

The Cortex‑M4 TPIU is specially designed for low-cost debug. It is a special version of the CoreSight™ TPIU. Your implementation can replace the Cortex‑M4 TPIU with other CoreSight components if your implementation requires the additional features of the CoreSight TPIU.

In this chapter, the term TPIU refers to the Cortex‑M4 TPIU. For information about the CoreSight TPIU, see the ARM® CoreSight™ Components Technical Reference Manual.

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