Sorry, your browser is not supported. We recommend upgrading your browser.
We have done our best to make all the documentation and resources available on old versions of Internet Explorer, but vector image support and the layout may not be optimal. Technical documentation is available as a PDF Download.
This chapter introduces the
Cortex®‑M4 processor and
instruction set, processor features and interfaces, configurable options, and product
About the processor
The Cortex®‑M4 processor is a low-power processor that features low gate count, low interrupt latency, and low-cost debug. The Cortex®‑M4 includes optional floating point arithmetic functionality. The processor is intended for deeply embedded applications that require fast interrupt response features.
The Cortex®‑M4 processor incorporates a processor core, Nested Vectored Interrupt Controller (NVIC), high-performance bus interfaces, a low-cost debug solution, and an optional Floating Point Unit (FPU).
The processor incorporates three external bus interfaces, an ETM interface that allows the connection of an Embedded Trace Macrocell, an AHB Trace Macrocell interface that enables simple connection of an ETM to the processor, and an Advanced High-performance Bus Access Port (AHB-AP) interface for debug accesses.
You can configure your Cortex®‑M4 implementation to include optional components, such as a Memory Protection Unit (MPU), a Flash Patch and Breakpoint Unit (FPB), and a Data Watchpoint and Trace Unit (DWT).
Documentation provided with this product includes a Technical Reference Manual, an Integration and Implementation manual, together with design flow, architecture, and protocol information.
A description of the differences in functionality between product revisions.