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Arm Cortex‑M1 DesignStart FPGA-Xilinx edition User Guide : Cortex‑M1 processor signals

Cortex®‑M1 processor signals

The External AHB-Lite interface is not exported, and the AXI interface replaces it. For more information, see the AHB master bus to AXI bridge signal connections figure in the PrimeCell® Infrastructure AMBA®2 AHB to AMBA®3 AXI Bridges (BP136) Technical Overview.

The AHB-AP interface is not exported, it is replaced by the Serial Wire (SW) or JTAG interface pins that are described in the Arm® CoreSight™ SoC-400 Technical Reference Manual.

Note

The PrimeCell® Infrastructure AMBA®2 AHB to AMBA®3 AXI Bridges (BP136) Technical Overview document is a superseded, indicating that the documentation is no longer maintained, but the current content is still relevant.
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