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Arm Cortex‑M1 DesignStart FPGA-Xilinx edition User Guide : Debug tab

Debug tab

The following figure shows the Debug tab.

Figure 3-2 Debug tab

Debug tab

On this tab you can select the following:

Debug port select
You can select either JTAG, Serial Wire (SW), or JTAG and SW

Note

Any debug port that is implemented on the processor needs to be connected to a debug probe using I/O pins. This is generally a separate interface to the FPGA JTAG port.
If the optional V2C-DAPLink board is fitted, the example design connects Serial Wire Debug (SWD) to this board.
Small Debug
If small debug is enabled the processor debug logic has reduced functionality, but with the benefit of reduced resource usage.

The differences are:

  • The full debug configuration has four breakpoint comparators and two watchpoint comparators.
  • The small debug configuration has two breakpoint comparators and one watchpoint comparator.
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