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Arm Cortex‑M1 DesignStart FPGA-Xilinx edition User Guide : Instruction Memory tab

Instruction Memory tab

The following figure shows the Instruction Memory tab.

Figure 3-3 Instruction Memory tab

On this tab you can select the following:

The range is 8KB to 1MB. Select the optimal size for your code base.


  • Currently the flow to update a bitstream with new Instruction Tightly Coupled Memory (ITCM) data only supports memory sizes in the range 16KB to 128KB. If you require sizes outside that range, contact Arm for support.
Initialize ITCM
If you require the instruction memory to be initialized when the design is built:
  1. Select Initialize ITCM.
  2. Specify the filename, see the example design as a reference.


    • The filename must not have quote marks around it.
    • The filename must be added to the design and marked as a memory initialization file.
    • Vivado reads the memory file during synthesis. It is not possible to update the memory file and to run just implementation or generate bitstream. To incorporate software updates into an existing bit file, see Software Update flow.

ITCM aliasing is controlled at reset by the state of the CFGITCMEN[1:0] signal. The upper and lower aliases can be enabled independently, that is, either one alias, both aliases, or none of the aliases. For more information about processor memory regions, see the Cortex®‑M1 Technical Reference Manual.

To boot the processor from ITCM, you must:

  1. Enable ITCM lower alias.
  2. Initialize the ITCM.

If the processor does not boot from ITCM, you must provide memory at address 0x00000000 on the external AXI interface which contains the initial stack pointer and vector table.

Instruction fetch latency is lower from ITCM than from the AXI interface. If you boot from AXI memory, you can copy code to ITCM at the upper alias and then execute from there to get better performance.

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