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Arm Cortex‑M1 DesignStart FPGA-Xilinx edition User Guide : V2C-DAPLink adaptor board features

V2C-DAPLink adaptor board features

The board supports the following features:

  • Allows Arty Artix 7 (A7) and Spartan-7 (S7) FPGA boards to be used with mbed OS 2 Classic.
  • V2C-DAPLink Serial Wire Debug (SWD) over USB.
  • UART over USB.
  • Dedicated Quad Serial Port Interface (QSPI) flash for code image.
  • Micro-SD card for application use (SPI mode only).
  • Allows stacking of standard Shield expansion boards.
  • DAPLink USB Composite Device:
    • USB Mass Storage Device Class (MSC) for programming software images to block RAM and QSPI.
    • USB Communication Device Class (CDC) for UART debug with nSRST support.
    • USB Human Interface Device (HID) for CMSIS-DAP software debug.

The following figure shows the V2C-DAPLink adaptor board, the Arty header breakout pins, and the point where they are interfaced together (this is depicted in orange).

Figure 5-1 V2C-DAPLink adaptor board

A dedicated microcontroller on the V2C-DAPLink board provides the interface between a micro-USB connector and the UART and Serial Wire Debug (SWD) interfaces. This is pre-loaded with firmware that is configured to permit drag-and-drop software download onto the on-board QSPI. Using this programming interface requires that the Xilinx QSPI controllers are implemented as shown in the example design (at the same memory locations). The flash programming routine is loaded into target RAM at address 0x10000000, which is the Instruction Tightly Coupled Memory (ITCM) upper alias. The V2C-DAPLink firmware is not intended to work with any processor except a single Cortex®‑M1 instance as demonstrated in the example design. For more information on the flash programming routine and download requirements, see Flash download requirements.

The V2C-DAPLink board has a reset switch for the Cortex‑M1 processor, CS_nSRST, this reset is also driven from the V2C-DAPLink chip. CS_nSRST must be used to reset the processor nSYSRESET and peripherals, but not the processor DBGRESETn or the Debug Access Port (DAP) resets.

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