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Debug tab

The following figure shows the Debug tab.

Figure 3-2 Debug tab

On this tab you can select the following:

Debug port select

You can select either JTAG, Serial Wire (SW), JTAG and SW, or No Debug.


Any debug port that is implemented on the processor needs to be connected to a debug probe using I/O pins. This is generally a separate interface to the FPGA JTAG port.

If the optional V2C-DAPLink board is fitted, the example design connects Serial Wire Debug (SWD) to this board.

Small Debug
If small debug is enabled the processor debug logic has reduced functionality, but with the benefit of reduced resource usage.

The differences are:

  • The full debug configuration has four breakpoint comparators and two watchpoint comparators.
  • The small debug configuration has two breakpoint comparators and one watchpoint comparator.
No debug

When No Debug is selected the debug port is removed from the processor core. This allows a resource-optimized build to be created of the core. Also, when No Debug is selected, consider the following:

  • The Small Debug option is disabled.
  • All debug pins are removed from the processor instance (JTAG, SW, and debug resets).
  • The ability to drag-and-drop new code using the V2C-DAPLink board is no longer supported. For more information, see Programming the V2C-DAPLink QSPI using drag and drop. However, if the V2C-DAPLink J2 jumper (Cfg) is fitted, existing code is still run from the V2C-DAPLink QSPI device.
  • The ability to debug the processor core is removed. For more information, see Using the μVision debugger to communicate through V2C-DAPLink .
  • The ability to download software projects through the V2C-DAPLink board is no longer supported.
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