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Arm Cortex‑M33 Devices Generic User Guide : Cortex‑M33 instructions

Cortex®‑M33 instructions

The T32 instruction set is supported by the Cortex®‑M33 processor.

Note

In the following table:

  • Angle brackets, <>, enclose alternative forms of the operand.
  • Braces, {}, enclose optional operands.
  • The Operands column is not exhaustive.
  • Op2 is a flexible second operand that can be either a register or a constant.
  • Most instructions can use an optional condition code suffix.

For more information on the instructions and operands, see the instruction descriptions.

Table 3-1 Cortex‑M33 instruction set summary

Mnemonic Operands Brief description Flags Page
ADC, ADCS {Rd,} Rn, Op2 Add with Carry N,Z,C,V ADD, ADC, SUB, SBC, and RSB
ADD, ADDS {Rd,} Rn, Op2 Add N,Z,C,V ADD, ADC, SUB, SBC, and RSB
ADD, ADDW {Rd,} Rn, #imm12 Add - ADD, ADC, SUB, SBC, and RSB
ADR Rd, label Address to Register - ADR
AND, ANDS {Rd,} Rn, Op2 Logical AND N,Z,C AND, ORR, EOR, BIC, and ORN
ASR, ASRS Rd, Rm, <Rs|#n> Arithmetic Shift Right N,Z,C ASR, LSL, LSR, ROR, and RRX
B {cond} label Branch {conditionally} - B, BL, BX, and BLX
BFC Rd, #lsb, #width Bit Field Clear - BFC and BFI
BFI Rd, Rn, #lsb, #width Bit Field Insert - BFC and BFI
BIC, BICS {Rd,} Rn, Op2 Bit Clear N,Z,C AND, ORR, EOR, BIC, and ORN
BKPT #imm8 Breakpoint - BKPT
BL label Branch with Link - B, BL, BX, and BLX
BLX Rm Branch indirect with Link and Exchange - B, BL, BX, and BLX
BLXNS Rm Branch indirect with Link and Exchange, Non-secure - BXNS and BLXNS
BX Rm Branch and Exchange - B, BL, BX, and BLX
BXNS Rm Branch and Exchange, Non-secure - BXNS and BLXNS
CBNZ Rn, label Compare and Branch on Non Zero - CBZ and CBNZ
CBZ Rn, label Compare and Branch on Zero - CBZ and CBNZ
CDP, CDP2 {cond} coproc, #op1, Rt, CRn, CRm{, #op2} Coprocessor Data Processing - CDP and CDP2
CLREX - Clear Exclusive - CLREX
CLZ Rd, Rm Count Leading Zeros - CLZ
CMN Rn, Op2 Compare Negative N,Z,C,V CMP and CMN
CMP Rn, Op2 Compare N,Z,C,V CMP and CMN
CPSID i Change Processor State, Disable Interrupts - CPS
CPSIE i Change Processor State, Enable Interrupts - CPS
DMB {opt} Data Memory Barrier - DMB
DSB {opt} Data Synchronization Barrier - DSB
EOR, EORS {Rd,} Rn, Op2 Exclusive OR N,Z,C AND, ORR, EOR, BIC, and ORN
FLDMDBX ,FLDMIAX Rn FLDMX (Decrement Before, Increment After) loads - FLDMDBX, FLDMIAX
FSTMDBX,FSTMIAX Rn FSTMX (Decrement Before, Increment After) stores - FSTMDBX, FSTMIAX
ISB {opt} Instruction Synchronization Barrier - ISB
IT - If Then condition block - IT
LDA Rd, [Rn] Load-Acquire Word   LDA and STL
LDAB Rd, [Rn] Load-Acquire Byte   LDA and STL
LDAEX Rd, [Rn] Load-Acquire Exclusive Word - LDAEX and STLEX
LDAEXB Rd, [Rn] Load-Acquire Exclusive Byte - LDAEX and STLEX
LDAEXH Rd, [Rn] Load-Acquire Exclusive Halfword - LDAEX and STLEX
LDAH Rd, [Rn] Load-Acquire Halfword - LDA and STL
LDM Rn{!}, reglist Load Multiple - LDM and STM
LDMDB, LDMEA Rn{!}, reglist Load Multiple Decrement Before - LDM and STM
LDMIA, LDMFD Rn{!}, reglist Load Multiple, Increment After - LDM and STM
LDR Rt, [Rn, Rm {, LSL #shift}] Load Register Word (register offset) - LDR and STR, register offset
LDR Rt, label Load Register Word (literal) - LDR, PC‑relative
LDR, LDRT Rt, [Rn, #offset] Load Register Word (immediate offset, unprivileged) - LDR and STR, immediate offset, LDR and STR, unprivileged
LDRB Rt, [Rn, Rm {, LSL #shift}] Load Register Byte (register offset) - LDR and STR, register offset
LDRB Rt, label Load Register Byte (literal) - LDR, PC‑relative
LDRB, LDRBT Rt, [Rn, #offset] Load Register Byte (immediate offset, unprivileged) - LDR and STR, immediate offset, LDR and STR, unprivileged
LDRD Rt, Rt2, [Rn, #offset] Load Register Dual (immediate offset) - LDR and STR, immediate offset
LDRD Rt, Rt2, label Load Register Dual (PC- relative) - LDR, PC‑relative
LDREX Rt, [Rn, #offset] Load Register Exclusive - LDREX and STREX
LDREXB Rt, [Rn] Load Register Exclusive Byte - LDREX and STREX
LDREXH Rt, [Rn] Load Register Exclusive Halfword - LDREX and STREX
LDRH Rt, [Rn, Rm {, LSL #shift}] Load Register Halfword (register offset) - LDR and STR, register offset
LDRH Rt, label Load Register Halfword (literal) - LDR, PC‑relative
LDRH, LDRHT Rt, [Rn, #offset] Load Register Halfword (immediate offset, unprivileged) - LDR and STR, immediate offset, LDR and STR, unprivileged
LDRSB Rt, [Rn, Rm {, LSL #shift}] Load Register Signed Byte (register offset) - LDR and STR, register offset
LDRSB Rt, label Load Register Signed Byte (PC-relative) - LDR, PC‑relative
LDRSB, LDRSBT Rt, [Rn, #offset] Load Register Signed Byte (immediate offset, unprivileged) - LDR and STR, immediate offset, LDR and STR, unprivileged
LDRSH Rt, [Rn, Rm {, LSL #shift}] Load Register Signed Halfword (register offset) - LDR and STR, register offset
LDRSH Rt, label Load Register Signed Halfword (PC-relative) - LDR, PC‑relative
LDRSH, LDRSHT Rt, [Rn, #offset] Load Register Signed Halfword (immediate offset, unprivileged) - LDR and STR, immediate offset, LDR and STR, unprivileged
LSL, LSLS Rd, Rm, <Rs|#n> Logical Shift Left N,Z,C ASR, LSL, LSR, ROR, and RRX
LSR, LSRS Rd, Rm, <Rs|#n> Logical Shift Right N,Z,C ASR, LSL, LSR, ROR, and RRX
MCR,MCR2 {cond} coproc, #opc1, Rt, CRn, CRm{, #opc2} Move to Coprocessor from Register - MCR and MCR2
MCRR,MCRR2 {cond} coproc, #opc1, Rt, Rt2, CRm Move to Coprocessor from two Registers - MCRR and MCRR2
MLA Rd, Rn, Rm, Ra Multiply Accumulate - MUL, MLA, and MLS
MLS Rd, Rn, Rm, Ra Multiply and Subtract - MUL, MLA, and MLS
MOV, MOVS Rd, Op2 Move N,Z,C MOV and MVN
MOV, MOVS Rd, Rm Move (register) N,Z MOV and MVN
MOVT Rd, #imm16 Move Top - MOVT
MOVW Rd, #imm16 Move 16-bit constant N,Z,C MOV and MVN
MRC,MRC2 {cond} coproc, #opc1, Rt, CRn, CRm{, #opc2} Move to Register from |Coprocessor - MRC and MRC2
MRRC,MRRC2 {cond} coproc, #opc1, Rt, Rt2, CRm Move to two Registers from Coprocessor. - MRRC and MRRC2
MRS Rd, spec_reg Move from Special Register to general register - MRS
MSR spec_reg, Rn Move from general register to Special Register - MSR
MUL, MULS {Rd,} Rn, Rm Multiply N,Z MUL, MLA, and MLS
MVN, MVNS Rd, Op2 Bitwise NOT N,Z,C MOV and MVN
NOP - No Operation - NOP
ORN, ORNS {Rd,} Rn, Op2 Logical OR NOT N,Z,C AND, ORR, EOR, BIC, and ORN
ORR, ORRS {Rd,} Rn, Op2 Logical OR N,Z,C AND, ORR, EOR, BIC, and ORN
PKHTB, PKHBT {Rd,} Rn, Rm, {, Op2} Pack Halfword - PKHBT and PKHTB
PLD [Rn {, #offset}] Preload Data - PLD
POP reglist Pop registers from stack - PUSH and POP
PUSH reglist Push registers onto stack - PUSH and POP
QADD {Rd,} Rn, Rm Saturating Add Q QADD and QSUB
QADD16 {Rd,} Rn, Rm Saturating Add 16 - QADD and QSUB
QADD8 {Rd,} Rn, Rm Saturating Add 8 - QADD and QSUB
QASX {Rd,} Rn, Rm Saturating Add and Subtract with Exchange - QASX and QSAX
QDADD {Rd,} Rn, Rm Saturating Double and Add Q QDADD and QDSUB
QDSUB {Rd,} Rn, Rm Saturating Double and Subtract Q QDADD and QDSUB
QSAX {Rd,} Rn, Rm Saturating Subtract and Add with Exchange - QASX and QSAX
QSUB {Rd,} Rn, Rm Saturating Subtract Q QADD and QSUB
QSUB16 {Rd,} Rn, Rm Saturating Subtract 16 - QADD and QSUB
QSUB8 {Rd,} Rn, Rm Saturating Subtract 8 - QADD and QSUB
RBIT Rd, Rn Reverse Bits - REV, REV16, REVSH, and RBIT
REV Rd, Rn Reverse byte order in a word - REV, REV16, REVSH, and RBIT
REV16 Rd, Rn Reverse byte order in each halfword - REV, REV16, REVSH, and RBIT
REVSH Rd, Rn Reverse byte order in bottom halfword and sign extend - REV, REV16, REVSH, and RBIT
ROR, RORS Rd, Rm, <Rs|#n> Rotate Right N,Z,C ASR, LSL, LSR, ROR, and RRX
RRX, RRXS Rd, Rm Rotate Right with Extend N,Z,C ASR, LSL, LSR, ROR, and RRX
RSB, RSBS {Rd,} Rn, Op2 Reverse Subtract N,Z,C,V ADD, ADC, SUB, SBC, and RSB
SADD16 {Rd,} Rn, Rm Signed Add 16 GE SADD16 and SADD8
SADD8 {Rd,} Rn, Rm Signed Add 8 GE SADD16 and SADD8
SASX {Rd,} Rn, Rm Signed Add and Subtract with Exchange GE SASX and SSAX
SBC, SBCS {Rd,} Rn, Op2 Subtract with Carry N,Z,C,V ADD, ADC, SUB, SBC, and RSB
SBFX Rd, Rn, #lsb, #width Signed Bit Field Extract - SBFX and UBFX
SDIV {Rd,} Rn, Rm Signed Divide - SDIV and UDIV
SEL {Rd,} Rn, Rm Select bytes GE SEL
SEV - Send Event - SEV
SG - Secure Gateway - SG
SHADD16 {Rd,} Rn, Rm Signed Halving Add 16 - SHADD16 and SHADD8
SHADD8 {Rd,} Rn, Rm Signed Halving Add 8 - SHADD16 and SHADD8
SHASX {Rd,} Rn, Rm Signed Halving Add and Subtract with Exchange - SHASX and SHSAX
SHSAX {Rd,} Rn, Rm Signed Halving Subtract and Add with Exchange - SHASX and SHSAX
SHSUB16 {Rd,} Rn, Rm Signed Halving Subtract 16 - SHSUB16 and SHSUB8
SHSUB8 {Rd,} Rn, Rm Signed Halving Subtract 8 - SHSUB16 and SHSUB8
SMLABB, SMLABT, SMLATB, SMLATT Rd, Rn, Rm, Ra Signed Multiply Accumulate halfwords Q SMLAWB, SMLAWT, SMLABB, SMLABT, SMLATB, and SMLATT
SMLAD, SMLADX Rd, Rn, Rm, Ra Signed Multiply Accumulate Dual Q SMLAD and SMLADX
SMLAL RdLo, RdHi, Rn, Rm Signed Multiply Accumulate Long (32 × 32 + 64), 64-bit result - UMULL, UMAAL, UMLAL, SMULL, and SMLAL
SMLALBB, SMLALBT, SMLALTB, SMLALTT RdLo, RdHi, Rn, Rm Signed Multiply Accumulate Long, halfwords - SMLALD, SMLALDX, SMLALBB, SMLALBT, SMLALTB, and SMLALTT
SMLALD, SMLALDX RdLo, RdHi, Rn, Rm Signed Multiply Accumulate Long Dual - SMLALD, SMLALDX, SMLALBB, SMLALBT, SMLALTB, and SMLALTT
SMLAWB, SMLAWT Rd, Rn, Rm, Ra Signed Multiply Accumulate, word by halfword Q SMLAWB, SMLAWT, SMLABB, SMLABT, SMLATB, and SMLATT
SMLSD, SMLSDX Rd, Rn, Rm, Ra Signed Multiply Subtract Dual Q SMLSD and SMLSLD
SMLSLD, SMLSLDX RdLo, RdHi, Rn, Rm Signed Multiply Subtract Long Dual - SMLSD and SMLSLD
SMMLA, SMMLAR Rd, Rn, Rm, Ra Signed Most Significant Word Multiply Accumulate - SMMLA and SMMLS
SMMLS, SMMLSR Rd, Rn, Rm, Ra Signed Most Significant Word Multiply Subtract - SMMLA and SMMLS
SMMUL, SMMULR Rd, Rn, Rm Signed Most Significant Word Multiply - SMMUL
SMUAD, SMUADX {Rd,} Rn, Rm Signed Dual Multiply Add Q. SMUAD and SMUSD
SMULBB, SMULBT, SMULTB, SMULTT {Rd,} Rn, Rm Signed Multiply (halfwords) - SMUL and SMULW
SMULL RdLo, RdHi, Rn, Rm Signed Multiply Long (32 × 32), 64-bit result - UMULL, UMAAL, UMLAL, SMULL, and SMLAL
SMULWB, SMULWT {Rd,} Rn, Rm Signed Multiply word by halfword - SMUL and SMULW
SMUSD, SMUSDX {Rd,} Rn, Rm Signed Dual Multiply Subtract - SMUAD and SMUSD
SSAT Rd, #n, Rm {,shift #s} Signed Saturate Q SSAT and USAT
SSAT16 Rd, #n, Rm Signed Saturate 16 Q SSAT16 and USAT16
SSAX {Rd,} Rn, Rm Signed Subtract and Add with Exchange GE SASX and SSAX
SSUB16 {Rd,} Rn, Rm Signed Subtract 16 GE SSUB16 and SSUB8
SSUB8 {Rd,} Rn, Rm Signed Subtract 8 GE SSUB16 and SSUB8
STL Rt, [Rn] Store-Release Word - LDA and STL
STLB Rt, [Rn] Store-Release Byte - LDA and STL
STLEX Rt, Rt [Rn] Store-Release Exclusive Word - LDAEX and STLEX
STLEXB Rt, Rt [Rn] Store-Release Exclusive Byte - LDAEX and STLEX
STLEXH Rt, Rt [Rn] Store-Release Exclusive Halfword - LDAEX and STLEX
STLH Rt, [Rn] Store-Release Halfword - LDA and STL
STM Rn{!}, reglist Store Multiple - LDM and STM
STMDB, STMEA Rn{!}, reglist Store Multiple Decrement Before - LDM and STM
STMIA, STMFD Rn{!}, reglist Store Multiple Increment After - LDM and STM
STR Rt, [Rn, Rm {, LSL #shift}] Store Register Word (register offset) - LDR and STR, register offset
STR, STRT Rt, [Rn, #offset] Store Register Word (immediate offset, unprivileged) - LDR and STR, immediate offset, LDR and STR, unprivileged
STRB Rt, [Rn, Rm {, LSL #shift}] Store Register Byte (register offset) - LDR and STR, register offset
STRB, STRBT Rt, [Rn, #offset] Store Register Byte (immediate offset, unprivileged) - LDR and STR, immediate offset, LDR and STR, unprivileged
STRD Rt, Rt2, [Rn, #offset] Store Register Dual two words - LDR and STR, immediate offset
STREX Rd, Rt, [Rn, #offset] Store Register Exclusive - LDREX and STREX
STREXB Rd, Rt, [Rn] Store Register Exclusive Byte - LDREX and STREX
STREXH Rd, Rt, [Rn] Store Register Exclusive Halfword - LDREX and STREX
STRH Rt, [Rn, Rm {, LSL #shift}] Store Register Halfword (register offset) - LDR and STR, register offset
STRH, STRHT Rt, [Rn, #offset] Store Register Halfword (immediate offset, unprivileged) - LDR and STR, immediate offset, LDR and STR, unprivileged
SUB, SUBS {Rd,} Rn, Op2 Subtract N,Z,C,V ADD, ADC, SUB, SBC, and RSB
SUB, SUBW {Rd,} Rn, #imm12 Subtract - ADD, ADC, SUB, SBC, and RSB
SVC #imm Supervisor Call - SVC
SXTAB {Rd,} Rn, Rm {,ROR #n} Sign extend 8 bits to 32 and Add - SXTA and UXTA
SXTAB16 {Rd,} Rn, Rm {,ROR #n} Sign extend two 8-bit values to 16 and Add - SXTA and UXTA
SXTAH {Rd,} Rn, Rm {,ROR #n} Sign extend 16 bits to 32 and Add - SXTA and UXTA
SXTB Rd, Rm {,ROR #n} Sign extend 8 bits to 32 - SXT and UXT
SXTB16 {Rd,} Rm {,ROR #n} Sign extend 8 bits to 16 - SXT and UXT
SXTH {Rd,} Rm {,ROR #n} Sign extend a Halfword to 32 - SXT and UXT
TBB [Rn, Rm] Table Branch Byte - TBB and TBH
TBH [Rn, Rm, LSL #1] Table Branch Halfword - TBB and TBH
TEQ Rn, Op2 Test Equivalence N,Z,C TST and TEQ
TST Rn, Op2 Test N,Z,C TST and TEQ
TT Rd, [Rn] Test Target - TT, TTT, TTA, and TTAT
TTA Rd, [Rn] Test Target Alternate Domain - TT, TTT, TTA, and TTAT
TTAT Rd, [Rn] Test Target Alternate Domain Unprivileged - TT, TTT, TTA, and TTAT
TTT Rd, [Rn] Test Target Unprivileged - TT, TTT, TTA, and TTAT
UADD16 {Rd,} Rn, Rm Unsigned Add 16 GE UADD16 and UADD8
UADD8 {Rd,} Rn, Rm Unsigned Add 8 GE UADD16 and UADD8
UASX {Rd,} Rn, Rm Unsigned Add and Subtract with Exchange GE UASX and USAX
UBFX Rd, Rn, #lsb, #width Unsigned Bit Field Extract - SBFX and UBFX
UDF {c}{q} {#}imm Permanently Undefined. - UDF
UDIV {Rd,} Rn, Rm Unsigned Divide - SDIV and UDIV
UHADD16 {Rd,} Rn, Rm Unsigned Halving Add 16 - UHADD16 and UHADD8
UHADD8 {Rd,} Rn, Rm Unsigned Halving Add 8 - UHADD16 and UHADD8
UHASX {Rd,} Rn, Rm Unsigned Halving Add and Subtract with Exchange - UHASX and UHSAX
UHSAX {Rd,} Rn, Rm Unsigned Halving Subtract and Add with Exchange - UHASX and UHSAX
UHSUB16 {Rd,} Rn, Rm Unsigned Halving Subtract 16 - UHSUB16 and UHSUB8
UHSUB8 {Rd,} Rn, Rm Unsigned Halving Subtract 8 - UHSUB16 and UHSUB8
UMAAL RdLo, RdHi, Rn, Rm Unsigned Multiply Accumulate Accumulate Long (32 × 32 + 32 + 32), 64-bit result - UMULL, UMAAL, UMLAL, SMULL, and SMLAL
UMLAL RdLo, RdHi, Rn, Rm Unsigned Multiply Accumulate Long (32 × 32 + 64), 64-bit result - UMULL, UMAAL, UMLAL, SMULL, and SMLAL
UMULL RdLo, RdHi, Rn, Rm Unsigned Multiply Long (32 × 32), 64-bit result - UMULL, UMAAL, UMLAL, SMULL, and SMLAL
UQADD16 {Rd,} Rn, Rm Unsigned Saturating Add 16 - UQADD and UQSUB
UQADD8 {Rd,} Rn, Rm Unsigned Saturating Add 8 - UQADD and UQSUB
UQASX {Rd,} Rn, Rm Unsigned Saturating Add and Subtract with Exchange - UQASX and UQSAX
UQSAX {Rd,} Rn, Rm Unsigned Saturating Subtract and Add with Exchange - UQASX and UQSAX
UQSUB16 {Rd,} Rn, Rm Unsigned Saturating Subtract 16 - UQADD and UQSUB
UQSUB8 {Rd,} Rn, Rm Unsigned Saturating Subtract 8 - UQADD and UQSUB
USAD8 {Rd,} Rn, Rm Unsigned Sum of Absolute Differences - USAD8
USADA8 Rd, Rn, Rm, Ra Unsigned Sum of Absolute Differences and Accumulate - USADA8
USAT Rd, #n, Rm{,shift #s}, Ra Unsigned Saturate Q SSAT and USAT
USAT16 Rd, #n, Rm Unsigned Saturate 16 Q SSAT16 and USAT16
USAX {Rd,} Rn, Rm Unsigned Subtract and Add with Exchange GE UASX and USAX
USUB16 {Rd,} Rn, Rm Unsigned Subtract 16 GE USUB16 and USUB8
USUB8 {Rd,} Rn, Rm Unsigned Subtract 8 GE USUB16 and USUB8
UXTAB {Rd,} Rn, Rm {,ROR #n} Rotate, unsigned extend 8 bits to 32 and Add - SXTA and UXTA
UXTAB16 {Rd,} Rn, Rm {,ROR #n} Rotate, unsigned extend two 8-bit values to 16 and Add - SXTA and UXTA
UXTAH {Rd,} Rn, Rm {,ROR #n} Rotate, unsigned extend and Add Halfword - SXTA and UXTA
UXTB Rd, Rm {,ROR #n} Unsigned zero-extend Byte - SXT and UXT
UXTB16 {Rd,} Rm {,ROR #n} Unsigned zero-extend Byte 16 - SXT and UXT
UXTH Rd, Rm {,ROR #n} Unsigned zero-extend Halfword - SXT and UXT
VABS .F32 Sd, Sm Floating-point Absolute - VABS
VADD .F32 {Sd,} Sn, Sm Floating-point Add - VADD
VCMP .F32 Sd, <<Sm| #0.0> Compare two floating-point registers, or one floating-point register and zero N,Z,C,V VCMP and VCMPE
VCMPE .F32 Sd, <<Sm| #0.0> Compare two floating-point registers, or one floating-point register and zero with Invalid Operation check N,Z,C,V VCMP and VCMPE
VCVT .F32.Tm <Sd>, Sm Convert from floating-point to integer - VCVT and VCVTR between floating-point and integer
VCVT .Td.F32 Sd, Sd, #fbits Convert from floating-point to fixed point - VCVT between floating-point and fixed-point
VCVTA .Tm.F32 <Sd>, Sm Convert from floating-point to integer with directed rounding to nearest with Ties Away - VCVTA, VCVTM VCVTN, and VCVTP
VCVTB VCVTT .F32.F16 Sd, Sm Convert half-precision value to single-precision or double-precision - VCVTB and VCVTT
VCVTB VCVTT .F16.F32 Sd, Sm Convert single-precision or double-precision register to half-precision - VCVTB and VCVTT
VCVTM .Tm.F32 <Sd>, Sm Convert from floating-point to integer with directed rounding towards Minus infinity - VCVTA, VCVTM VCVTN, and VCVTP
VCVTN .Tm.F32 <Sd>, Sm Convert from floating-point to integer with directed rounding to nearest with Ties to even - VCVTA, VCVTM VCVTN, and VCVTP
VCVTP .Tm.F32 <Sd>, Sm Convert from floating-point to integer with directed rounding towards Plus infinity - VCVTA, VCVTM VCVTN, and VCVTP
VCVTR .Tm.F32 <Sd>, Sm Convert between floating-point and integer with rounding. - VCVT and VCVTR between floating-point and integer
VDIV .F32 {Sd,} Sn, Sm Floating-point Divide - VDIV
VFMA .F32 {Sd,} Sn, Sm Floating-point Fused Multiply Accumulate - VFMA and VFMS
VFMS .F32 {Sd,} Sn, Sm Floating-point Fused Multiply Subtract - VFMA and VFMS
VFNMA .F32 {Sd,} Sn, Sm Floating-point Fused Negate Multiply Accumulate - VFNMA and VFNMS
VFNMS .F32 {Sd,} Sn, Sm Floating-point Fused Negate Multiply Subtract - VFNMA and VFNMS
VLDM {mode}{.size} Rn{!}, list Floating-point Load Multiple extension registers - VLDM
VLDR .F32 Sd, [<Rn> {, #offset}] Floating-point Load an extension register from memory (immediate) - VLDR
VLDR .F32 Sd, <label> Load an extension register from memory - VLDR
VLDR .F32 Sd, [PC,#-0] Load an extension register from memory - VLDR
VLLDM <c> Rn Floating-point Lazy Load multiple - VLLDM
VLSTM <c> Rn Floating-point Lazy Store multiple - VLSTM
VMAXNM .F32 Sd, Sn, Sm Maximum of two floating-point numbers with IEEE754-2008 NaN handling - VMAXNM and VMINNM
VMINNM .F32 Sd, Sn, Sm Minimum of two floating-point numbers with IEEE754-2008 NaN handling - VMAXNM and VMINNM
VMLA .F32 Sd, Sn, Sm Floating-point Multiply Accumulate - VMLA and VMLS
VMLS .F32 Sd, Sn, Sm Floating-point Multiply Subtract - VMLA and VMLS
VMOV <Sn|Rt>, <Rt|Sn> Copy core register to single-precision - VMOV core register to single-precision
VMOV <Sm|Rt>, <Sm1|Rt2>, <Rt|Sm>, <Rt2|Sm1> Copy two core registers to two single-precision - VMOV two core registers to two single-precision registers
VMOV {.size} Dd[x], Rt Copy core register to scalar - VMOV core register to scalar
VMOV {.dt} Rt, Dn[x] Copy scalar to core register - VMOV scalar to core register
VMOV .F32 Sd, #immm Floating-point Move immediate - VMOV Immediate
VMOV .F32 Sd, Sd, Sm Copies the contents of one register to another - VMOV Register
VMOV <Dm|Rt>, <Rt|Rt2>, <Rt2|Dm> Floating-point Move transfers two words between two core registers and a doubleword register - VMOV two core registers and a double-precision register
VMRS Rt, FPSCR Move to core register from floating-point Special Register N,Z,C,V VMRS
VMSR FPSCR, Rt Move to floating-point Special Register from core register - VMSR
VMUL .F32 {Sd,} Sn, Sm Floating-point Multiply - VMUL
VNEG .F32 Sd, Sm Floating-point Negate - VNEG
VNMLA .F32 Sd, Sn, Sm Floating-point Multiply Accumulate and Negate - VNMLA, VNMLS and VNMUL
VNMLS .F32 Sd, Sn, Sm Floating-point Multiply, Subtract and Negate - VNMLA, VNMLS and VNMUL
VNMUL .F32 {Sd,} Sn, Sm Floating-point Multiply and Negate - VNMLA, VNMLS and VNMUL
VPOP {.size} list Load multiple consecutive floating-point registers from the stack - VPOP
VPUSH {.size} list Store multiple consecutive floating-point registers to the stack - VPUSH
VRINTA .F32 Sd, Sm Float to integer in floating-point format conversion with directed rounding to Nearest with Ties Away - VRINTA, VRINTN, VRINTP, VRINTM, and VRINTZ
VRINTM .F32 Sd, Sm Float to integer in floating-point format conversion with directed rounding to Minus infinity - VRINTA, VRINTN, VRINTP, VRINTM, and VRINTZ
VRINTN .F32 Sd, Sm Float to integer in floating-point format conversion with directed rounding to Nearest with Ties to even - VRINTA, VRINTN, VRINTP, VRINTM, and VRINTZ
VRINTP .F32 Sd, Sm Float to integer in floating-point format conversion with directed rounding to Plus infinity - VRINTA, VRINTN, VRINTP, VRINTM, and VRINTZ
VRINTR .F32 Sd, Sm Float to integer in floating-point format conversion with rounding towards value specified in FPSCR - VRINTR and VRINTX
VRINTX .F32 Sd, Sm Float to integer in floating-point format conversion with rounding specified in FPSCR - VRINTR and VRINTX
VRINTZ .F32 Sd, Sm Float to integer in floating-point format conversion with rounding towards Zero - VRINTA, VRINTN, VRINTP, VRINTM, and VRINTZ
VSEL .F32 Sd, Sn, Sm Select register, alternative to a pair of conditional VMOV - VSEL
VSQRT .F32 Sd, Sm Calculates floating-point Square Root - VSQRT
VSTM {mode}{.size} Rn{!}, list Floating-point Store Multiple - VSTM
VSTR .F32 Sd, [Rn{, #offset}] Floating-point Store Register stores an extension register to memory - VSTR
VSUB F32 {Sd,} Sn, Sm Floating-point Subtract - VSUB
WFE - Wait For Event - WFE
WFI - Wait For Interrupt - WFI
YIELD - Suspend task - YIELD
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