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Functional Description

Table of Contents

About the Cortex®‑A35 processor
Implementation options
Supported standards and specifications
Test features
Design tasks
Product revisions
Technical Overview
About system control
About the Generic Timer
About the memory model
Clocks, Resets, and Input Synchronization
Input synchronization
Power Management
Power domains
Power modes
Core Wait for Interrupt
Core Wait for Event
L2 Wait for Interrupt
Powering down an individual core
Powering up an individual core
Powering down the processor without system driven L2 flush
Powering up the processor without system driven L2 flush
Powering down the processor with system driven L2 flush
Powering up the processor with system driven L2 flush
Entering Dormant mode
Exiting Dormant mode
Event communication using WFE or SEV
Communication to the Power Management Controller
Cache Behavior and Cache Protection
Cached memory types
Coherency between data caches with the MOESI protocol
Cache misses, unexpected cache hits, and speculative fetches
Disabling a cache
Invalidating or cleaning a cache
About read allocate mode
About cache protection
Error reporting
Error injection
L1 Memory System
About the L1 memory system
TLB Organization
Program flow prediction
About the internal exclusive monitor
About data prefetching
L2 Memory System
About the L2 memory system
Snoop and maintenance requests
Support for memory types
Memory type information exported from the processor
Handling of external aborts
AXI Master Interface
About the AXI master interface
AXI privilege information
AXI transactions
Attributes of the AXI master interface
ACE Master Interface
About the ACE master interface
ACE configurations
ACE privilege information
ACE transactions
Attributes of the ACE master interface
Snoop channel properties
AXI compatibility mode
CHI Master Interface
About the CHI master interface
CHI configurations
Attributes of the CHI master interface
CHI channel properties
CHI transactions
ACP Slave Interface
About the ACP
Transfer size support
ACP performance
ACP user signals
GIC CPU Interface
Bypassing the GIC CPU Interface
Memory map for the GIC CPU interface
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