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Revisions

This section describes the technical changes between released issues of this book.

Table C-1 Issue 0000-00

Change Location Affects

First release for r0p0.

- -

Table C-2 Issue 0001-00

Change Location Affects

Product name udpated from the Mercury processor to the Cortex-A35 processor.

Everywhere the product name is used. All versions

First release for r0p1, revision information updated.

Main ID Register, EL1.

CPU Interface Identification Register.

VM CPU Interface Identification Register.

External Debug Peripheral Identification Register 1.

ROM Table Peripheral Identification Register 2.

Performance Monitors Peripheral Identification Register 2.

Trace ID Register.

ETM Peripheral Identification Register 2.

CTI Peripheral Identification Register 2.

r0p1

References to CP15DISABLE signal removed.

AArch32 register summary.

Primary Region Remap Register.

Reset Management Register.

System Control Register.

All versions

CPUID/Way [20:18] bit field description updated.

CPU Memory Error Syndrome Register.

CPU Memory Error Syndrome Register, EL1.

All versions

Memory Error Syndrome Register.

Memory Error Syndrome Register, EL1.

All versions

CCSIDR and CCSIDR_EL1 encodings table updated.CPUID/Way [21:18] bit field description updated.

Cache Size ID Register.

Cache Size ID Register, EL1.

All versions

ICB [31:30] bit field description updated.

LoUIS [23:21] bit field updated.

Cache Level ID Register.

Cache Level ID Register, EL1.

All versions

DYNSDIS [11] bit updated.

CPU Auxiliary Control Register. All versions

Several reset values updated in summary tables.

c9 registers.

AArch32 Performance monitor registers.

AArch64 Performance monitor registers.

All versions

PMU events added to PMU events table.

Performance monitoring events. All versions

DTAH [24] bit updated.

CPU Auxiliary Control Register, EL1. All versions

ROM table for v7 added.

ROM entry registers. All versions

Table C-4 Issue 0100-00

Change Location Affects

First release for r1p0

Revision history table

Main ID Register, EL1 and Main ID Register

CPU Interface Identification Register.

VM CPU Interface Identification Register.

ROM Table Peripheral Identification Register 2.

Performance Monitors Peripheral Identification Register 2.

ETM Peripheral Identification Register 2.

CTI Peripheral Identification Register 2.

MIDR and VPIDR reset values in c0 registers and AArch32 Identification registers.

MIDR_EL1 and VPIDR_EL2 reset values in AArch64 Identification registers.

GICV_IIDR reset value in Virtual CPU interface register summary.

GICC_IIDR reset value in CPU interface register summary.

r1p0
Updated company name from Arm to Arm Entire manual All versions
Updated all sections affected by the addition of a new asymmetric floating-point/NEON feature r1p0
Updated all sections affected by the additional of the CP15SDISABLE2 signal r1p0
Fixed incorrect MRC/MCR encodings Performance Monitors Control Register All versions
Clarified the L2 cache behavior when disabled Disabling a cache All versions
Added warm reset information Resets All versions
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