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ATB interface signals

The ATB bus supports clock and data handling signals when the processor includes an ATB interface for each core to output trace information for debugging.

This interface exists only if the processor is configured to have one or more ETMs.

You must balance all ATB interface signals with respect to CLKIN and time them relative to ATCLKEN.

Table A-44 ATB interface signals

Signal Direction Description
ATCLKEN Input ATB clock enable
ATREADYMx Input ATB device ready
AFVALIDMx Input FIFO flush request
ATDATAMx[31:0] Output Data
ATVALIDMx Output Data valid
ATBYTESMx[1:0] Output Data size
AFREADYMx Output FIFO flush finished
ATIDMx[6:0] Output Trace source ID
SYNCREQMx Input Synchronization request from the trace sink
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