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AXI interface signals

The AXI protocol supports clock, configuration, and data handling signals when the processor uses this protocol for the master memory interface.

This interface exists only if the processor is configured to have the AXI interface.

All AXI channels must be balanced with respect to CLKIN and timed relative to ACLKENM.

Table A-18 AXI clock and configuration signals

Signal Direction Description
ACLKENM Input AXI Master bus clock enable. See Clocks for more information.
RDMEMATTR[7:0] Output Read request memory attributes.
WRMEMATTR[7:0] Output Write request memory attributes.

Table A-19 AXI write address channel signals

Signal Direction Description
AWADDRM[39:0] Output Write address.
AWBURSTM[1:0] Output

Write burst type.

AWCACHEM[3:0] Output

Write cache type.

AWIDM[4:0] Output Write address ID.
AWLENM[7:0] Output

Write burst length.


Write lock type.

AWPROTM[2:0] Output

Write protection type.


Write address ready.

AWSIZEM[2:0] Output

Write burst size.


Write address valid.

Table A-20 AXI write data channel signals

Signal Direction Description
WDATAM[127:0] Output Write data
WIDM[4:0] Output Write data ID
WLASTM Output Write data last transfer indication
WREADYM Input Write data ready
WSTRBM[15:0] Output Write byte-lane strobes
WVALIDM Output Write data valid

Table A-21 AXI write data response channel signals

Signal Direction Description
BIDM[4:0] Input Write response ID
BREADYM Output Write response ready
BRESPM[1:0] Input Write response
BVALIDM Input Write response valid

Table A-22 AXI read address channel signals

Signal Direction Description
ARADDRM[39:0] Output

Read address.

ARBURSTM[1:0] Output

Read burst type.

ARCACHEM[3:0] Output

Read cache type

ARIDM[5:0] Output Read address ID
ARLENM[7:0] Output

Read burst length


Read lock type

ARPROTM[2:0] Output

Read protection type


Read address ready

ARSIZEM[2:0] Output

Read burst size


Read address valid

Table A-23 AXI read data channel signals

Signal Direction Description
RDATAM[127:0] Input Read data
RIDM[5:0] Input Read data ID
RLASTM Input Read data last transfer indication
RREADYM Output Read data ready
RRESPM[1:0] Input Read data response
RVALIDM Input Read data valid
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