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CHI interface signals

The CHI protocol supports clock, configuration, data handling, and address map signals when the processor uses this protocol for the master memory interface.

This interface exists only if the processor is configured to have the CHI interface.

Table A-34 CHI clock and configuration signals

Signal Direction Description
SCLKEN Input CHI interface bus clock enable
SINACT Input CHI snoop active
NODEID[6:0] Input Cortex®‑A35 CHI Node Identifier
RXSACTIVE Input Receive pending activity indicator
TXSACTIVE Output Transmit pending activity indicator
RXLINKACTIVEREQ Input Receive link active request
RXLINKACTIVEACK Output Receive link active acknowledge
TXLINKACTIVEREQ Output Transmit link active request
TXLINKACTIVEACK Input Transmit link active acknowledge
REQMEMATTR[7:0] Output Request memory attributes

Table A-35 CHI transmit request virtual channel signals

Signal Direction Description
TXREQFLITPEND Output Transmit request flit pending
TXREQFLITV Output Transmit request flit valid
TXREQFLIT[99:0] Output Transmit request flit payload
TXREQLCRDV Input Transmit request link-layer credit valid

Table A-36 CHI transmit response virtual channel signals

Signal Direction Description
TXRSPFLITPEND Output Transmit response flit pending
TXRSPFLITV Output Transmit response flit valid
TXRSPFLIT[44:0] Output Transmit response flit
TXRSPLCRDV Input Transmit response link-layer credit valid

Table A-37 CHI transmit data virtual channel signals

Signal Direction Description
TXDATFLITPEND Output Transmit data flit pending
TXDATFLITV Output Transmit data flit valid
TXDATFLIT[193:0] Output Transmit data flit
TXDATLCRDV Input Transmit data link-layer credit valid

Table A-38 CHI receive snoop virtual channel signals

Signal Direction Description
RXSNPFLITPEND Input Receive snoop flit pending
RXSNPFLITV Input Receive snoop flit valid
RXSNPFLIT[64:0] Input Receive snoop flit
RXSNPLCRDV Output Receive snoop link-layer credit valid

Table A-39 CHI receive response virtual channel signals

Signal Direction Description
RXRSPFLITPEND Input Receive response flit pending
RXRSPFLITV Input Receive response flit valid
RXRSPFLIT[44:0] Input Receive response flit
RXRSPLCRDV Output Receive response link-layer credit valid

Table A-40 CHI receive Data virtual channel signals

Signal Direction Description
RXDATFLITPEND Input Receive data flit pending
RXDATFLITV Input Receive data flit valid
RXDATFLIT[193:0] Input Receive data flit
RXDATLCRDV Output Receive data link-layer credit valid

Table A-41 CHI system address map signals

Signal Direction Description
SAMADDRMAP0[1:0] Input Region mapping, 0 - 512MB
SAMADDRMAP1[1:0] Input Region mapping, 512MB - 1GB
SAMADDRMAP2[1:0] Input Region mapping, 1GB - 1.5GB
SAMADDRMAP3[1:0] Input Region mapping, 1.5GB - 2GB
SAMADDRMAP4[1:0] Input Region mapping, 2GB - 2.5GB
SAMADDRMAP5[1:0] Input Region mapping, 2.5GB - 3GB
SAMADDRMAP6[1:0] Input Region mapping, 3GB - 3.5GB
SAMADDRMAP7[1:0] Input Region mapping, 3.5GB - 4GB
SAMADDRMAP8[1:0] Input Region mapping, 4GB - 8GB
SAMADDRMAP9[1:0] Input Region mapping, 8GB - 16GB
SAMADDRMAP10[1:0] Input Region mapping, 16GB - 32GB
SAMADDRMAP11[1:0] Input Region mapping, 32GB - 64GB
SAMADDRMAP12[1:0] Input Region mapping, 64GB - 128GB
SAMADDRMAP13[1:0] Input Region mapping, 128GB - 256GB
SAMADDRMAP14[1:0] Input Region mapping, 256GB - 512GB
SAMADDRMAP15[1:0] Input Region mapping, 512GB - 1TB
SAMMNBASE[39:24] Input

MN base address

SAMMNBASE must reside in a SAMADDRMAPx[1:0] that corresponds to the HN-I.

SAMMNNODEID[6:0] Input MN node ID
SAMHNI0NODEID[6:0] Input HN-I 0 node ID
SAMHNI1NODEID[6:0] Input HN-I 1 node ID
SAMHNF0NODEID[6:0] Input HN-F 0 node ID
SAMHNF1NODEID[6:0] Input HN-F 1 node ID
SAMHNF2NODEID[6:0] Input HN-F 2 node ID
SAMHNF3NODEID[6:0] Input HN-F 3 node ID
SAMHNF4NODEID[6:0] Input HN-F 4 node ID
SAMHNF5NODEID[6:0] Input HN-F 5 node ID
SAMHNF6NODEID[6:0] Input HN-F 6 node ID
SAMHNF7NODEID[6:0] Input HN-F 7 node ID
SAMHNFMODE[2:0] Input HN-F interleaving module
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