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Debug

Table of Contents

Debug
About debug methods
Debug access
Effects of resets on debug registers
External access permissions to debug registers
Debug events
Debug memory map
Debug signals
Changing the authentication signals for debug
PMU
About the PMU
External register access permissions to the PMU registers
Performance monitoring events
PMU interrupts
Exporting PMU events
ETM
About the ETM
Configuration options for the ETM unit and trace resources
Resetting the ETM
Programming and reading ETM trace unit registers
CTI
About the cross-trigger
Cross-trigger inputs and outputs
Direct access to internal memory
About direct access to internal memory
Encoding for tag and data in the L1 instruction cache
Encoding for tag and data in the L1 data cache
Encoding for the main TLB RAM
Encoding for walk cache
Encoding for IPA cache
AArch32 debug registers
AArch32 debug register summary
Debug Breakpoint Control Registers
Debug Watchpoint Control Registers
Debug ID Register
Debug Device ID Register
Debug Device ID Register 1
AArch64 debug registers
AArch64 debug register summary
Debug Breakpoint Control Registers, EL1
Debug Watchpoint Control Registers, EL1
Memory-mapped debug registers
Memory-mapped debug register summary
External Debug Reserve Control Register
External Debug Integration Mode Control Register
External Debug Device ID Register 0
External Debug Device ID Register 1
External Debug Processor Feature Register
External Debug Feature Register
External Debug Peripheral Identification Registers
External Debug Peripheral Identification Register 0
External Debug Peripheral Identification Register 1
External Debug Peripheral Identification Register 2
External Debug Peripheral Identification Register 3
External Debug Peripheral Identification Register 4
External Debug Peripheral Identification Register 5-7
External Debug Component Identification Registers
External Debug Component Identification Register 0
External Debug Component Identification Register 1
External Debug Component Identification Register 2
External Debug Component Identification Register 3
ROM table
About the ROM table
ROM table register interface
ROM table register summary
ROM entry registers
ROM Table Peripheral Identification Registers
ROM Table Peripheral Identification Register 0
ROM Table Peripheral Identification Register 1
ROM Table Peripheral Identification Register 2
ROM Table Peripheral Identification Register 3
ROM Table Peripheral Identification Register 4
ROM Table Peripheral Identification Register 5-7
ROM Table Component Identification Registers
ROM Table Component Identification Register 0
ROM Table Component Identification Register 1
ROM Table Component Identification Register 2
ROM Table Component Identification Register 3
PMU registers
AArch32 PMU register summary
Performance Monitors Control Register
Performance Monitors Common Event Identification Register 0
Performance Monitors Common Event Identification Register 1
AArch64 PMU register summary
Performance Monitors Control Register, EL0
Performance Monitors Common Event Identification Register 0, EL0
Performance Monitors Common Event Identification Register 1, EL0
Memory-mapped PMU register summary
Performance Monitors Configuration Register
Performance Monitors Peripheral Identification Registers
Performance Monitors Peripheral Identification Register 0
Performance Monitors Peripheral Identification Register 1
Performance Monitors Peripheral Identification Register 2
Performance Monitors Peripheral Identification Register 3
Performance Monitors Peripheral Identification Register 4
Performance Monitors Peripheral Identification Register 5-7
Performance Monitors Component Identification Registers
Performance Monitors Component Identification Register 0
Performance Monitors Component Identification Register 1
Performance Monitors Component Identification Register 2
Performance Monitors Component Identification Register 3
ETM registers
ETM register summary
Programming Control Register
Status Register
Trace Configuration Register
Branch Broadcast Control Register
Auxiliary Control Register
Event Control 0 Register
Event Control 1 Register
Stall Control Register
Global Timestamp Control Register
Synchronization Period Register
Cycle Count Control Register
Trace ID Register
ViewInst Main Control Register
ViewInst Include-Exclude Control Register
ViewInst Start-Stop Control Register
Sequencer State Transition Control Registers 0-2
Sequencer Reset Control Register
Sequencer State Register
External Input Select Register
Counter Reload Value Registers 0-1
Counter Control Register 0
Counter Control Register 1
Counter Value Registers 0-1
ID Register 8
ID Register 9
ID Register 10
ID Register 11
ID Register 12
ID Register 13
Implementation Specific Register 0
ID Register 0
ID Register 1
ID Register 2
ID Register 3
ID Register 4
ID Register 5
Resource Selection Control Registers 2-16
Single-Shot Comparator Control Register 0
Single-Shot Comparator Status Register 0
OS Lock Access Register
OS Lock Status Register
Power Down Control Register
Power Down Status Register
Address Comparator Value Registers 0-7
Address Comparator Access Type Registers 0-7
Context ID Comparator Value Register 0
VMID Comparator Value Register 0
Context ID Comparator Control Register 0
Integration ATB Identification Register
Integration Instruction ATB Data Register
Integration Instruction ATB In Register
Integration Instruction ATB Out Register
Integration Mode Control Register
Claim Tag Set Register
Claim Tag Clear Register
Device Affinity Register 0
Device Affinity Register 1
Software Lock Access Register
Software Lock Status Register
Authentication Status Register
Device Architecture Register
Device ID Register
Device Type Register
ETM Peripheral Identification Registers
ETM Peripheral Identification Register 0
ETM Peripheral Identification Register 1
ETM Peripheral Identification Register 2
ETM Peripheral Identification Register 3
ETM Peripheral Identification Register 4
ETM Peripheral Identification Register 5-7
ETM Component Identification Registers
ETM Component Identification Register 0
ETM Component Identification Register 1
ETM Component Identification Register 2
ETM Component Identification Register 3
CTI registers
Cross trigger register summary
External register access permissions to the CTI registers
CTI Device Identification Register
CTI Integration Mode Control Register
CTI Peripheral Identification Registers
CTI Peripheral Identification Register 0
CTI Peripheral Identification Register 1
CTI Peripheral Identification Register 2
CTI Peripheral Identification Register 3
CTI Peripheral Identification Register 4
CTI Peripheral Identification Register 5-7
CTI Component Identification Registers
CTI Component Identification Register 0
CTI Component Identification Register 1
CTI Component Identification Register 2
CTI Component Identification Register 3
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