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Register Descriptions

Table of Contents

AArch32 system registers
AArch32 register summary
c0 registers
c1 registers
c2 registers
c3 registers
c4 registers
c5 registers
c6 registers
c7 registers
c7 system operations
c8 system operations
c9 registers
c10 registers
c11 registers
c12 registers
c13 registers
c14 registers
c15 registers
64-bit registers
AArch32 Identification registers
AArch32 Virtual memory control registers
AArch32 Fault handling registers
AArch32 Other System control registers
AArch32 Address registers
AArch32 Thread registers
AArch32 Performance monitor registers
AArch32 Secure registers
AArch32 Virtualization registers
AArch32 GIC system registers
AArch32 Generic Timer registers
AArch32 Implementation defined registers
Auxiliary Control Register
Auxiliary Data Fault Status Register
Auxiliary ID Register
Auxiliary Instruction Fault Status Register
Auxiliary Memory Attribute Indirection Register 0
Auxiliary Memory Attribute Indirection Register 1
Configuration Base Address Register
Cache Size ID Register
Cache Level ID Register
Architectural Feature Access Control Register
CPU Auxiliary Control Register
CPU Extended Control Register
CPU Memory Error Syndrome Register
Cache Size Selection Register
Cache Type Register
Domain Access Control Register
Data Fault Address Register
Data Fault Status Register
DFSR with Short-descriptor translation table format
DFSR with Long-descriptor translation table format
Encoding of ISS[24:20] when HSR[31:30] is 0b00
FCSE Process ID Register
Hyp Auxiliary Configuration Register
Hyp Auxiliary Control Register
Hyp Auxiliary Data Fault Status Syndrome Register
Hyp Auxiliary Instruction Fault Status Syndrome Register
Hyp Auxiliary Memory Attribute Indirection Register 0
Hyp Auxiliary Memory Attribute Indirection Register 1
Hyp Architectural Feature Trap Register
Hyp Configuration Register
Hyp Configuration Register 2
Hyp Debug Control Register
Hyp Data Fault Address Register
Hyp Instruction Fault Address Register
Hyp IPA Fault Address Register
Hyp System Control Register
Hyp Syndrome Register
Hyp System Trap Register
Hyp Translation Control Register
Hyp Vector Base Address Register
Auxiliary Feature Register 0
Debug Feature Register 0
Instruction Set Attribute Register 0
Instruction Set Attribute Register 1
Instruction Set Attribute Register 2
Instruction Set Attribute Register 3
Instruction Set Attribute Register 4
Instruction Set Attribute Register 5
Memory Model Feature Register 0
Memory Model Feature Register 1
Memory Model Feature Register 2
Memory Model Feature Register 3
Processor Feature Register 0
Processor Feature Register 1
Instruction Fault Address Register
Instruction Fault Status Register
IFSR with Short-descriptor translation table format
IFSR with Long-descriptor translation table format
Interrupt Status Register
L2 Auxiliary Control Register
L2 Control Register
L2 Extended Control Register
L2 Memory Error Syndrome Register
Memory Attribute Indirection Registers 0 and 1
Main ID Register
Multiprocessor Affinity Register
Non-Secure Access Control Register
Normal Memory Remap Register
Physical Address Register
Primary Region Remap Register
Revision ID Register
Reset Management Register
Secure Configuration Register
System Control Register
Secure Debug Control Register
Secure Debug Enable Register
TCM Type Register
TLB Type Register
Translation Table Base Control Register
TTBCR with Short-descriptor translation table format
TTBCR with Long-descriptor translation table format
Translation Table Base Register 0
TTBR0 with Short-descriptor translation table format
TTBR0 with Long-descriptor translation table format
Translation Table Base Register 1
TTBR1 with Short-descriptor translation table format
TTBR1 with Long-descriptor translation table format
Vector Base Address Register
Virtualization Multiprocessor ID Register
Virtualization Processor ID Register
Virtualization Translation Control Register
AArch64 system registers
AArch64 register summary
AArch64 Identification registers
AArch64 Exception handling registers
AArch64 Virtual memory control registers
AArch64 Other System control registers
AArch64 Cache maintenance operations
AArch64 TLB maintenance operations
AArch64 Address translation operations
AArch64 Miscellaneous operations
AArch64 Performance monitor registers
AArch64 Reset registers
AArch64 Secure registers
AArch64 Virtualization registers
AArch64 EL2 TLB maintenance operations
AArch64 GIC system registers
AArch64 Generic Timer registers
AArch64 Thread registers
AArch64 Implementation defined registers
Auxiliary Control Register, EL1
Auxiliary Control Register, EL2
Auxiliary Control Register, EL3
Auxiliary Fault Status Register 0, EL1, EL2, and EL3
Auxiliary Fault Status Register 1, EL1, EL2, and EL3
Auxiliary ID Register, EL1
Auxiliary Memory Attribute Indirection Register, EL1
Auxiliary Memory Attribute Indirection Register, EL2
Auxiliary Memory Attribute Indirection Register, EL3
Configuration Base Address Register, EL1
Cache Size ID Register, EL1
Cache Level ID Register, EL1
Architectural Feature Access Control Register, EL1
Architectural Feature Trap Register, EL2
Architectural Feature Trap Register, EL3
Cache Size Selection Register, EL1
Cache Type Register, EL0
CPU Auxiliary Control Register, EL1
CPU Extended Control Register, EL1
CPU Memory Error Syndrome Register, EL1
Domain Access Control Register, EL2
Data Cache Zero ID Register, EL0
Exception Syndrome Register, EL1
Exception Syndrome Register, EL2
Exception Syndrome Register, EL3
Fault Address Register, EL1
Fault Address Register, EL2
Fault Address Register, EL3
Hyp Auxiliary Configuration Register, EL2
Hypervisor Configuration Register, EL2
Hypervisor IPA Fault Address Register, EL2
Hyp System Trap Register, EL2
AArch64 Debug Feature Register 0, EL1
AArch64 Instruction Set Attribute Register 0, EL1
AArch64 Memory Model Feature Register 0, EL1
AArch64 Processor Feature Register 0, EL1
AArch32 Auxiliary Feature Register 0, EL1
AArch32 Debug Feature Register 0, EL1
AArch32 Instruction Set Attribute Register 0, EL1
AArch32 Instruction Set Attribute Register 1, EL1
AArch32 Instruction Set Attribute Register 2, EL1
AArch32 Instruction Set Attribute Register 3, EL1
AArch32 Instruction Set Attribute Register 4, EL1
AArch32 Instruction Set Attribute Register 5, EL1
AArch32 Memory Model Feature Register 0, EL1
AArch32 Memory Model Feature Register 1, EL1
AArch32 Memory Model Feature Register 2, EL1
AArch32 Memory Model Feature Register 3, EL1
AArch32 Processor Feature Register 0, EL1
AArch32 Processor Feature Register 1, EL1
Instruction Fault Status Register, EL2
IFSR32_EL2 with Short-descriptor translation table format
IFSR32_EL2 with Long-descriptor translation table format
Interrupt Status Register, EL1
L2 Auxiliary Control Register, EL1
L2 Control Register, EL1
L2 Extended Control Register, EL1
L2 Memory Error Syndrome Register, EL1
Memory Attribute Indirection Register, EL1
Memory Attribute Indirection Register, EL2
Memory Attribute Indirection Register, EL3
Monitor Debug Configuration Register, EL2
Monitor Debug Configuration Register, EL3
Monitor Debug System Control Register, EL1
Main ID Register, EL1
Multiprocessor Affinity Register, EL1
Physical Address Register, EL1
Revision ID Register, EL1
Reset Management Register, EL3
Reset Vector Base Address Register, EL3
Secure Configuration Register, EL3
System Control Register, EL1
System Control Register, EL2
System Control Register, EL3
Secure Debug Enable Register, EL3
Translation Control Register, EL1
Translation Control Register, EL2
Translation Control Register, EL3
Translation Table Base Register 0, EL1
Translation Table Base Register 1, EL1
Translation Table Base Register 0, EL3
Vector Base Address Register, EL1
Vector Base Address Register, EL2
Vector Base Address Register, EL3
Virtualization Multiprocessor ID Register, EL2
Virtualization Processor ID Register, EL2
Virtualization Translation Control Register, EL2
GIC registers
CPU interface register summary
Active Priority Register
CPU Interface Identification Register
Virtual interface control register summary
VGIC Type Register
Virtual CPU interface register summary
VM Active Priority Register
VM CPU Interface Identification Register
Generic Timer registers
Generic Timer register summary
AArch32 Generic Timer register summary
AArch64 Generic Timer register summary
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