You copied the Doc URL to your clipboard.

TBU interfaces

The following figure shows the TBU interfaces.

Figure 2-5 TBU interfaces


TBU TBS interface

The transaction slave (TBS) interface is an ACE5-Lite interface on which the TBU receives incoming untranslated memory accesses.

This interface supports a 64‑bit address width.

The interface implements optional signals to support the following AXI5 extensions:

  • Untranslated_Transactions.
  • Cache_Stash_Transactions.
  • DeAllocation_Transactions.
  • Low_Power_Signals.

    Note

    The TBS interface implements AWAKEUP to support the Low_Power_Signals extension. It does not support the other signals that AXI5 associates with this extension.

Note

The TBS interface does not support WriteEvict transactions, and therefore does not support the AWUNIQUE signal.

The TBS interface supports ACE Exclusive accesses.

If a transaction is terminated in the TBU, the transaction tracker returns the transaction with the user‑defined AXI RUSER and BUSER bits set to 0.

TBU TBM interface

The TBM transaction master interface is an ACE5‑Lite interface on which the TBU sends outgoing translated memory accesses.

The AXI ID of a transaction on this interface is the same as the AXI ID of the corresponding transaction on the TBS interface.

This interface supports a 64‑bit address width, and TBUCFG_DATA_WIDTH defines the data width.

This interface can issue read and write transactions until the outstanding transaction limit is reached. The MMU-600 provides parameters that permit you to configure:

  • The outstanding read transactions limit.
  • The outstanding write transactions limit.
  • The total outstanding read and write transactions limit.

The interface implements optional signals to support the following AXI5 extensions:

  • Untranslated_Transactions.
  • Cache_Stash_Transactions.
  • DeAllocation_Transactions.
  • Low_Power_Signals.

    Note

    The TBM interface implements AWAKEUP to support the Low_Power_Signals extension. It does not support the other signals that AXI5 associates with this extension.

Note

The TBM interface does not support WriteEvict transactions, and therefore does not support the AWUNIQUE signal.

When receiving an SLVERR or DECERR response to a downstream transaction, the TBM interface propagates the same response to the TBS interface.

The TBM interface supports ACE Exclusive accesses.

TBU LPI_PD interface

This Q‑Channel slave interface manages LPI powerdown for the TBU.

See the AMBA® Low Power Interface Specification, Arm® Q‑Channel and P‑Channel Interfaces for more information.

TBU LPI_CG interface

This Q‑Channel slave interface enables LPI clock‑gating for the TBU.

See the AMBA® Low Power Interface Specification, Arm® Q‑Channel and P‑Channel Interfaces for more information.

TBU DTI interface

The TBU DTI interface enables master devices with their own TLB and prefetch capability to request translations from the MMU-600. This interface uses the DTI‑TBU protocol for communication between the TBU and the TCU.

The TCU includes a slave DTI interface and each TBU includes a master DTI interface. To permit bidirectional communication, each DTI interface includes one AXI4‑Stream master interface and one AXI4‑Stream slave interface.

See the Arm® AMBA® Distributed Translation Interface (DTI) Protocol Specification and the Arm® AMBA® 4 AXI4-Stream Protocol Specification for more information.

TBU interrupt interfaces

This interface provides global, per-context, and performance interrupts.

TBU tie-off signals

The TBU tie-off signals enable you to initialize various operating parameters on exit from reset state.

At reset, the value of each tie-off signal controls the respective bits in the SMMU_IDR0 Register.

Was this page helpful? Yes No