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TBU tie-off signals

The TBU tie-off signals are sampled at reset. Ensure that the value of these signals does not change when the LPI_PD interface is not in the Q_STOPPED state.

The following table shows the TBU tie-off signals.

Table A-19 TBU tie-off signals

Signal

Direction

Description

ns_sid_high[23:TBUCFG_SID_WIDTH]

Input

Provides the high-order stream ID bits for all transactions with a Non-secure StreamID that pass through the TBU.

s_sid_high[23:TBUCFG_SID_WIDTH]

Input

Provides the high-order stream ID bits for all transactions with a Secure StreamID that pass through the TBU.

max_tok_trans[log2(TBUCFG_XLATE_SLOTS)-1:0]

Input

Indicates the number of DTI translation tokens to request when connecting to the TCU, minus 1.

pcie_mode

Input

You must tie this signal HIGH when the TBU is connected to a PCIe interface.

When this signal is HIGH, the TBU behaves as if the PCIe No Snoop property is applied to transactions downstream of the SMMU, provided that the PCIe interface outputs transactions with the following AXI memory types:

  • Normal Non-Cacheable Bufferable, when No Snoop is set for the transaction.
  • Write-Back, when No Snoop is not set for the transaction.

This TBU behavior is a requirement of the Arm Server Base System Architecture.

If this signal is HIGH, the attributes of TBS interface transactions are always combined with the translation attributes, even if stage 1 translation is enabled. That is, the transaction attributes are always calculated as if the DTI_TBU_TRANS_RESP.STRW field is EL1-S2, regardless of the actual STRW value.

If this signal is HIGH, the input attribute and shareability override information in the ATTR_OVR field of the DTI_TBU_TRANS_RESP message is ignored. For SMMUv3, PCIe masters do not support this feature.

sec_override

Input

When HIGH, certain registers are accessible to Non-secure accesses from reset, as the TCU_SCR register settings describe.

ecorevnum[3:0]

Input

Tie this signal to 0 unless directed otherwise by Arm.

utlb_roundrobin

Input

Defines the Micro TLB entry replacement policy.

When LOW, the Micro TLB uses a Pseudo Least Recently Used (PLRU) replacement policy. This policy typically provides the best average performance. However, when multiple translations are prefetched using a StashTranslation transaction, they might evict each other.

When HIGH, the Micro TLB uses a round-robin replacement policy. With this policy, you can prefetch multiple translations using a StashTranslation transaction without evictions occurring, as long as the Micro TLB size is not exceeded.

Tie this signal HIGH if a real-time upstream master prefetches translations and you want to avoid transactions evicting each other. Otherwise, tie this signal LOW.

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