Reliability, Availability, and Serviceability
Reliability, Serviceability, and Availability (RAS) features enable cache corruption to be detected and corrected, optionally generating interrupts into the system. All MMU-600 RAM-based caches support RAS error detection and correction.
The RAS Extension registers permit software to monitor the following caches for errors:
- TBU Main TLB (MTLB).
- TCU configuration cache.
- TCU translation table walk cache.
Within a coherent system, these caches are always clean, and there is no requirement to correct data on these caches. Any incorrect data is discarded and refetched. From an RAS standpoint, discarding and refetching counts as a corrected error.
See the Arm® System Memory Management Unit Architecture Specification, SMMU architecture version 3.0 and version 3.1 for more information.