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The MMU-600 provides the following features:

  • Compliance with the SMMUv3.1 architecture:
    • Support for Stage 1 translation, Stage 2 translation, and Stage 1 followed by stage 2 translation.
    • Support for ARMv8 AArch32 and AArch64 translation table formats.
    • Support for 4KB, 16KB and 64KB granule sizes in AArch64 format.
    • Masters can be stalled while a processor handles translation faults, enabling software support for demand paging.
    • Configuration tables in memory can support millions of active translation contexts.
    • Queues in memory perform MMU-600 management, no requirement to stall a processor when it accesses the MMU-600.
    • Support for PCI Express (PCIe) integration, including Address Translation Services (ATS) and Process Address Space IDs (PASIDs).
    • Support for Generic Interrupt Controller (GIC) integration, with Message Signaled Interrupts (MSIs) supported for common interrupt types.
    • A Performance Monitoring Unit (PMU) in each TBU and TCU that enables MMU-600 performance to be investigated.
    • Reliability, Serviceability and Availability (RAS) features for cache corruption detection and correction.
  • Support for AMBA® interfaces, including:
    • ACE5-Lite TBU transaction interfaces that support cache stash transactions, deallocating transactions, and cache maintenance.
    • An architected AXI5 extension that communicates per-transaction translation stream information.
    • An ACE5-Lite + Distributed Virtual Memory (DVM) TCU table walk interface that enables ARMv8.2 processors to perform shared TLB invalidate operations without accessing the MMU-600 directly.
    • An ACE5 Low Power extension that enables the TCU to subscribe to DVM TLB invalidate requests on powerup and powerdown without reprogramming the DTI interconnect.
    • AMBA DTI communication between the TCU and TBUs, enabling masters to request translations and implement TBU functionality internally.
    • Support for the AMBA Low-Power Interface (LPI) Q-Channel so that standard controllers can control power and clock gating.
    • AXI5 WAKEUP signaling on all interfaces, including DTI and APB interfaces.
  • Support for flexible integration:
    • A configurable number of TBUs can be placed close to the masters being translated.
    • Communication between TBU and TCU over AXI4-Stream, supported using the supplied DTI interconnect components, or any other AXI4-Stream interconnect.
    • DTI interconnect components support hierarchical topologies, and control of the tradeoff between number of wires and DTI bandwidth.
  • Support for high-performance translation:
    • Scalable configurable micro TLB and Main TLB in the TBU can reduce the number of translation requests to the TCU.
    • Optimization to store all architecturally defined page and block sizes, including contiguous page and block entries, as a single entry in the TBU and TCU TLBs.
    • Per-TBU prioritization in the TCU enable high-priority transaction streams to be translated before low-priority streams.
    • Hit-Under-Miss (HUM) support in the TBU enables transactions with different AXI IDs to be propagated out of order, when a translation is available.
    • TBU detection of multiple transactions that require the same translation so that only one TBU request to the TCU is required.
    • TCU detection of multiple translations that require the same table in memory so that only one TCU memory request is required.
    • Multi-level, multi-stage walk caches in the TCU reduce translation cost by performing only part of the table walk process on a miss.
    • A configurable number of concurrent translations in the TBU and TCU promotes high translation throughput.
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