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SMMUv3 support

The MMU-600 does not implement, or require, certain SMMUv3 functionality.

The SMMUv3 architectural registers include a set of ID registers that indicate the SMMUv3 features that the MMU-600 implements. The following table shows the SMMUv3 ID register values that the MMU-600 uses.


The values in this table are not configurable except for values that are specified in bold.

Table 2-18 MMU-600 SMMUv3 ID register architectural options




Description for value

SMMU_IDR0 S2P 1 Stage 2 translations are supported.
S1P 1 Stage 1 translations are supported.
TTF 0b11 Both AArch32 Long-descriptor and AArch64 translation tables are supported.
COHACC sup_cohacc Coherent access to translations, structure, and queues is supported.
BTM sup_btm Broadcast TLB maintenance is supported.
HTTU[1:0] 0b00 Updates of the Dirty state and Access flag are not supported.
DORMHINT 0 Dormant hint is not supported.
HYP 1 Hypervisor stage 1 context is supported.
ATS 1 PCIe Root Complex ATS is supported.
NS1ATS 1 Stage 1-only ATS is not supported.
ASID16 1 16-bit ASID is supported.
MSI 1 Message Signaled Interrupts (MSIs) are supported.
SEV sup_sev SMMU and system support for the generation of events.
ATOS 0 Address translation operations are not supported.
PRI 1 PCIe Page Request Interface (PRI) is supported.
VMW 1 VMID wildcard-matching is supported for TLB invalidation.
VMID16 1 16-bit VMIDs are supported.
CD2L 1 2-level Context Descriptor (CD) tables are supported.
VATOS 0 Virtual ATOS page interface is not supported.
TTENDIAN 0b00 Mixed-endian translation walks are supported.
STALL_MODEL {0, SMMU_S_CR0.NSSTALLD} Stall model and Terminate model are both supported, unless the Secure world disables Non-secure stalling.
TERM_MODEL 0 Terminated transactions can terminate with either RAZ/WI behavior or abort.
ST_LEVEL 0b01 2-level Stream tables are supported.
SMMU_IDR1 SIDSIZE 0b11000 24-bit stream IDs are supported.
SSIDSIZE 0b10100 20-bit substream IDs are supported.
PRIQS 0b10011 219 PRI queue entries are supported.
EVENTQS 0b10011 219 Event queue entries are supported.
CMDQS 0b10011 219 Command queue entries are supported.
ATTR_PERMS_OVR 1 Incoming permission attributes can be overridden.
ATTR_TYPES_OVR 1 Incoming memory attributes can be overridden.
REL 0 Base addresses are not fixed.
QUEUES_PRESET 0 The queue base addresses are not fixed.
TABLES_PRESET 0 The table base addresses are not fixed.
SMMU_IDR2 BA_VATOS 0 No VATOS page is present.
SMMU_IDR3 HAD 1 Hierarchical Attribute Disable is supported.

Page-Based Hardware Attributes are supported.


EL0/EL1 execute control distinction at stage 2 is supported for both AArch64 and AArch32 stage 2 translation tables.


If the request has a Process Address Space ID (PASID), the PASID is included in PRI queue overflow auto-generated responses. The STE.PPAR field is not checked and is treated as 1.

SMMU_IDR4 IMPDEF 0 No implementation defined features apply.
SMMU_IDR5 OAS sup_oas The size of the physical address that is output from the SMMU.
GRAN4K 1 4KB translation granule is supported.
GRAN16K 1 16KB translation granule is supported.
GRAN64K 1 64KB translation granule is supported.
VAX 0b00

Virtual addresses of 48 bits per CD.TTBx are supported.

STALL_MAX TCUCFG_XLATE_SLOTS Maximum number of outstanding stalled transactions that the SMMU supports.
SMMU_IIDR Implementer 0x43B Arm implementation.
Revision MAX(0x2, ecorevnum)

Minor revision is p2.


ecorevnum is not configurable.
Variant 0 Product variant, or major revision is r0.
ProductID 0x483 Arm ID.
SMMU_AIDR ArchMinorRev 0b0001 Architecture minor revision is SMMUv3.1.
ArchMajorRev 0b0000 Architecture major revision is SMMUv3.
SMMU_S_IDR0 MSI 1 Secure MSIs are supported.
STALL_MODEL 0b00 Stall model and Terminate model are both supported.
SMMU_S_IDR1 S_SIDSIZE 0b11000 24-bit Secure stream IDs are supported.
SECURE_IMPL 1 Security implemented.
SMMU_S_IDR3 SAMS 1 Secure Address Translation Services (ATS) maintenance is not implemented.

In an MMU-600-based system, the SFM_ERR global error cannot occur, because Service Failure Mode (SFM) is not required.

The MMU-600 accepts but does not act on the following SMMUv3 Prefetch commands:

Prefetch configuration. This command prefetches the required configuration for a StreamID.
Prefetch address. This command prefetches configuration and TLB entries for an address range.

The MMU-600 does not generate any of the following SMMUv3 events, because they are not required:

Unsupported Upstream Transaction.
TLB conflict.
Configuration cache conflict.
Speculative page request hint.
implementation defined event allocation.


F_TLB_CONFLICT and F_CFG_CONFLICT are not required because the MMU-600 caches include logic to ensure that only one entry can match at a time. If multiple cache entries match a transaction or translation request, only one entry is used and the others are ignored.

The MMU-600 never merges events. The STE.MEV field is ignored.

The TBU ignores the STE.ALLOCCFG field that the TCU communicates to the TBU in the ALLOCCFG field of the DTI_TBU_TRANS_RESP message.

The TCU sup_oas[2:0] signal must not be set to 0b110. If this value is used, the TCU treats it as 0b101, that is, 48 bits. The TBU supports a 48-bit PA size. The MMU-600 TBU and TCU cannot be used with other components that implement DTI and are configured for a 52-bit PA size.

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