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TBU direct indexing and MTLB partitioning

TBU direct indexing can help your system to meet real-time translation requirements by enabling the MMU-600 to manage Main TLB (MTLB) entries externally to the TBU.

Direct indexing enables real-time translation requirements to be met, as follows:

  • Prefetched entries can be guaranteed not to be overwritten by different streams.
  • The MTLB can be partitioned into different sets of entries that are used by different streams.

If you configure your system to not use direct indexing, you can select MTLB partitioning. MTLB partitioning has similar behavior, but only the most significant TLB index bits are provided, and the other bits are generated internally.

Direct indexing is enabled for a TBU when TBUCFG_DIRECT_IDX = 1.

When TBUCFG_DIRECT_IDX = 1, or when an MTLB is partitioned, aruser_m and awuser_m have more bits than the corresponding signals on the TBS interface. The following table shows the aruser_m and awuser_m extended bits.

Note

The table lists the extended bits in the order MSB first.

Table 2-12 Extended aruser_m and awuser_m bits for MTLB partitioning

Field name Width Description
mtlbidx

When direct indexing is enabled, the width of this field is log2(TBUCFG_MTLB_DEPTH) - 2.

When direct indexing is not enabled, the width of this field is 0.

MTLB index.
mtlbway

When direct indexing is enabled, the width of this field is 2.

When direct indexing is not enabled, the width of this field is 0.

MTLB way.
mtlbpart

log2(TBUCFG_MTLB_PARTS)

MTLB partition.
-

TBUCFG_AWUSER_WIDTH for awuser_m.

TBUCFG_ARUSER_WIDTH for aruser_m.

Regular AxUSER signals.

If an MTLB is partitioned:

  • The MTLB size is multiplied by TBUCFG_MTLB_PARTS.
  • The mtlbpart field defines the log2(TBUCFG_MTLB_PARTS) most significant index bits.

When direct indexing is enabled for a TBU:

  • Lookups and updates to the MTLB use the mtlbidx field.
  • Updates to the MTLB use the way that mtlbway specifies.
  • Lookups to the MTLB operate on all ways simultaneously.

To maintain system performance, Arm recommends that DVM invalidation is disabled on TBUs on which direct indexing is enabled. Disable DVM invalidation by setting the appropriate TCU_NODE_CTRLn.DIS_DVM bit.

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