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TCU transaction handling

The transaction width, burst length, and transfer size that the TCU supports depend on the transaction type.

The following table shows the TCU support for read transactions.

Table 2-13 TCU support for read transactions

Transaction type

Transaction width, bits

ARID[n:1]

ARID[0]

Stage 1 Stream table lookup 64 TCUCFG_PTW_SLOTS 1
Stream table lookup 256 TCUCFG_PTW_SLOTS 1
Translation table lookup 64 TCUCFG_PTW_SLOTS 1
Command queue read 128 All 0 0
DVM Complete - All 1 0

DVM Complete transactions are always one beat of full data width.

Command queue reads and DVM complete transactions are independent of translation slots. Therefore, the maximum number of read transactions that the TCU can issue at any time is TCUCFG_PTW_SLOTS + 2.

The following table shows the TCU support for write transactions.

Table 2-14 TCU support for write transactions

Transaction type

Transaction width, bits

AWID

Event queue write 256 0
PRI queue write 128 0

Message Signaled Interrupt (MSI)

32 0

Only one write transaction can be outstanding at a time.

All read and write transactions are aligned to the transaction size.

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