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TBU PMU Component and Peripheral ID Registers

The component and peripheral identity registers comply with the format used by Arm CoreLink and CoreSight components and recommended in the SMMUv3 architecture. They provide key information about the MMU-600 hardware, including the product and associated revision number. They also identify Arm as the designer of the SMMU.

These registers are all read-only. Each field defines a single byte in the least significant 8 bits, and the most significant 24 bits are reserved. The least significant 8 bits of the four Component ID registers form a single 32-bit conceptual ID register. In a similar way, the defined fields of the eight Peripheral ID registers form a conceptual 64-bit ID register.

Table 3-27 TBU PMU Component and Peripheral ID registers bit assignments

Register

Offset

Bits

Value

Function

SMMU_PMCG_PMAUTHSTATUS

0x02FB8

[7:0]

0x00

No authentication interface is implemented.

SMMU_PMCG_PIDR4

0x02FD0

[7:4]

0x0

4KB region count.

[3:0]

0x4

JEP106 continuation code for Arm.

SMMU_PMCG_PIDR5

0x02FD4

[7:0]

0x00

Reserved.

SMMU_PMCG_PIDR6

0x02FD8

[7:0]

0x00

Reserved.

SMMU_PMCG_PIDR7

0x02FDC

[7:0]

0x00

Reserved.

SMMU_PMCG_PIDR0

0x02FE0

[7:0]

0x83

Part number[7:0].

SMMU_PMCG_PIDR1

0x02FE4

[7:4]

0xB

JEP106 ID code[3:0] for Arm.

[3:0]

0x4

Part number[11:8].

SMMU_PMCG_PIDR2

0x02FE8

[7:4]

0x1

MMU-600 major revision.

The value 0x1 indicates major product revision r1.

[3]

0x1

The component uses a manufacturer identity code that JEDEC allocates, according to the JEP106 specification.

[2:0]

0x3

JEP106 ID code[6:4] for Arm.

SMMU_PMCG_PIDR3

0x02FEC

[7:4]

MAX[0x0,ecorevnum]

MMU-600 minor revision.

The value 0x0 indicates minor product revision p0.

[3:0]

0x0

CMOD. This field is not used.

SMMU_PMCG_CIDR0

0x02FF0

[7:0]

0x0D

Preamble.

SMMU_PMCG_CIDR1

0x02FF4

[7:0]

0x90

SMMU_PMCG_CIDR2

0x02FF8

[7:0]

0x05

SMMU_PMCG_CIDR3

0x02FFC

[7:0]

0xB1

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