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TBU_ERRGEN

This is the TBU Error Generation register. Use this register to generate tag parity errors. You might want to generate errors in certain cases, such as when testing error-handling software.

The TBU_ERRGEN characteristics are:

Usage constraints

When TBU_SCR.NS_RAS = 0, Non-secure accesses to this register are RAZ/WI.

Configurations

This register exists in all TBU configurations.

Attributes
Offset

0x08EC0

Type

RW

Reset

0x00000000

Width

64

The following figure shows the bit assignments.

Figure 3-17 TBU_ERRGEN register bit assignments


The following table shows the bit assignments.

Table 3-33 TBU_ERRGEN register bit assignments

Bits Name Function
[63:2] - Reserved.
[1] TMTLB

Main TLB tag parity error.

0No tag parity error is written to the Main TLB.
1Entries that are written to the Main TLB include a tag parity error. A fault occurs when the entry is used.
[0] DMTLB

Main TLB data parity error.

0No data parity error is written to the Main TLB.
1Entries that are written to the Main TLB include a data parity error. A fault occurs when the entry is used.

Note

Tag parity errors mask data parity errors. When testing data parity error functionality, ensure that software does not set this bit and the TMTLB bit at the same time.
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