DTI interconnect register slice signals
The DTI interconnect register slice provides signals for each of its interfaces.
The register slice provides an LPI_CG clock gating interface. The following table shows the LPI_CG signals.
Table A-29 DTI interconnect register slice LPI_CG interface signals
Signal |
Direction |
Description |
---|---|---|
qaccept_cg |
Output. |
Quiescence accept. |
qactive_cg |
Output. |
Component active. |
qdeny_cg |
Output. |
Quiescence deny. |
qreqn_cg |
Input. |
Quiescence request. |
The register slice provides a DN_S slave downstream interface. The following table shows the DN_S signals.
Table A-30 DTI interconnect register slice DN_S interface signals
Signal |
Direction |
Description |
---|---|---|
tvalid_dti_dn_s |
Slave to master. |
Flow control signal. |
tready_dti_dn_s |
Master to slave. |
Flow control signal. |
tdata_dti_dn_s |
Slave to master. |
Message data signal. |
tid_dti_dn_s |
Slave to master. |
Indicates the master that initiated the message. |
tlast_dti_dn_s |
Slave to master. |
Indicates the last cycle of a message. |
tkeep_dti_dn_s |
Slave to master. |
Indicates valid bytes. |
The register slice provides an UP_S slave upstream interface. The following table shows the UP_S signals.
Table A-31 DTI interconnect register slice UP_S interface signals
Signal |
Direction |
Description |
---|---|---|
tvalid_dti_up_s |
Master to slave. |
Flow control signal. |
tready_dti_up_s |
Slave to master. |
Flow control signal. |
tdata_dti_up_s |
Master to slave. |
Message data signal. |
tdest_dti_up_s |
Master to slave. |
Indicates the master that initiated the message. |
tlast_dti_up_s |
Master to slave. |
Indicates the last cycle of a message. |
tkeep_dti_up_s |
Master to slave. |
Indicates valid bytes. |
The register slice provides a DN_M master downstream interface. The following table shows the DN_M signals.
Table A-32 DTI interconnect register slice DN_M interface signals
Signal |
Direction |
Description |
---|---|---|
tvalid_dti_dn_m |
Slave to master. |
Flow control signal. |
tready_dti_dn_m |
Master to slave. |
Flow control signal. |
tdata_dti_dn_m |
Slave to master. |
Message data signal. |
tid_dti_dn_m |
Slave to master. |
Indicates the master that initiated the message. |
tlast_dti_dn_m |
Slave to master. |
Indicates the last cycle of a message. |
tkeep_dti_dn_m |
Slave to master. |
Indicates valid bytes. |
The register slice provides an UP_M master upstream interface. The following table shows the UP_M signals.
Table A-33 DTI interconnect register slice UP_M interface signals
Signal |
Direction |
Description |
---|---|---|
tvalid_dti_up_m |
Master to slave. |
Flow control signal. |
tready_dti_up_m |
Slave to master. |
Flow control signal. |
tdata_dti_up_m |
Master to slave. |
Message data signal. |
tdest_dti_up_m |
Master to slave. |
Indicates the master that initiated the message. |
tlast_dti_up_m |
Master to slave. |
Indicates the last cycle of a message. |
tkeep_dti_up_m |
Master to slave. |
Indicates valid bytes. |