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TBU tie-off signals

The TBU tie-off signals are sampled between exiting reset and the LPI_PD interface first entering the Q_RUN state. Ensure that the value of these signals does not change when the LPI_PD interface is in the Q_STOPPED or Q_EXIT state for the first time after exiting reset.

The following table shows the TBU tie-off signals.

Table A-19 TBU tie-off signals






Provides the high-order StreamID bits for all transactions with a Non-secure StreamID that pass through the TBU.



Provides the high-order StreamID bits for all transactions with a Secure StreamID that pass through the TBU.



Indicates the number of DTI translation tokens to request when connecting to the TCU, minus 1.



You must tie this signal HIGH when the TBU is connected to a PCIe interface.

When this signal is HIGH, the TBU behaves as if the PCIe 'No Snoop' property is applied to transactions downstream of the SMMU, as long as the PCIe interface outputs transactions with the following AXI memory types:

  • Normal Non-Cacheable Bufferable, when 'No Snoop' is set for the transaction.
  • Write-Back, when 'No Snoop' is not set for the transaction.

This TBU behavior is a requirement of the Arm Server Base System Architecture.

If this signal is HIGH, the attributes of TBS interface transactions are always combined with the translation attributes, even if stage 1 translation is enabled. That is, the transaction attributes are always calculated as if the DTI_TBU_TRANS_RESP.STRW field is EL1-S2, regardless of the actual STRW value.

If this signal is HIGH, the input attribute and shareability override information in the ATTR_OVR field of the DTI_TBU_TRANS_RESP message is ignored. For SMMUv3, PCIe masters do not support this feature.



When HIGH, certain registers are accessible to Non-secure accesses from reset, as the TCU_SCR register settings describe.



Tie this signal to 0 unless directed otherwise by Arm.



Defines the Micro TLB entry replacement policy.

When LOW, the Micro TLB uses a Pseudo Least Recently Used (PLRU) replacement policy. This policy typically provides the best average performance. However, when multiple translations are prefetched using a StashTranslation transaction, they might evict each other.

When HIGH, the Micro TLB uses a round-robin replacement policy. With this policy, you can prefetch multiple translations using a StashTranslation transaction without evictions occurring, as long as the Micro TLB size is not exceeded.

Tie this signal HIGH if a real-time upstream master prefetches translations and you want to avoid transactions evicting each other. Otherwise, tie this signal LOW.



Tie this signal HIGH to disable cache maintenance operations. When this signal is HIGH, the following transactions are always aborted with an SLVERR response:

  • CleanInvalid.
  • CleanShared.
  • CleanSharedPersist.
  • MakeInvalid.

Cache maintenance operations can sometimes break the requirements of limited sideband channel communication, such as when a master component accesses protected content. You can disable cache maintenance operations in such cases.

Cache maintenance operations are always disabled for ACE interfaces. This signal is therefore not present when the connected interface is configured as an ACE interface.


For ACE TBU configurations, this signal is not present, and is treated as 1.