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TCU and TBU test and debug signals

The test and debug signals are common to the TCU and TBU.

The following table shows the test and debug signals.

Table A-11 Test and debug signals

Signal

Direction

Description

dftcgen

Input

Clock gate enable.

To enable architectural clock gates for the aclk clock, set this signal HIGH during scan shift.

dftrstdisable

Input

Reset disable.

To disable reset, set this signal HIGH during scan shift.

dftramhold

Input

Preserve RAM state.

To preserve the state of the RAMs and their connected registers, set this signal HIGH during scan shift.

mbistresetn

Input

MBIST mode reset. This active-LOW signal is encoded as follows:

0Reset MBIST functional logic.
1Normal operation.

mbistreq

Input

MBIST test request. This signal is encoded as follows:

0Normal operation.
1Enable MBIST testing.
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