You copied the Doc URL to your clipboard.

Arm CoreLink MMU-600 System Memory Management Unit Technical Reference Manual : About the functions

About the functions

The major functional blocks of the MMU-600 are the TBU, TCU, and DTI interconnect.

The following figure shows an example system that uses the MMU-600.

Figure 2-1 Example system with the MMU-600

The MMU-600 contains the following key components:

Translation Buffer Unit (TBU)
The TBU contains Translation Lookaside Buffers (TLBs) that cache translation tables. The MMU-600 implements at least one TBU for each connected master, and these TBUs are local to the corresponding master.
Translation Control Unit (TCU)
The TCU controls and manages the address translations. The MMU-600 implements a single TCU. In MMU-600-based systems, the AMBA® DTI protocol defines the standard for communicating with the TCU.
DTI interconnect
The DTI interconnect connects multiple TBUs to the TCU.

When an MMU-600 TBU receives a transaction on the TBS interface, it looks for a matching translation in its TLBs. If it has a matching translation, it uses it to translate the transaction and outputs the transaction on the TBM interface. If it does not have a matching translation, it requests a new translation from the TCU using the DTI interface.

When the TCU receives a DTI translation request, it uses the QTW interface to perform:

  • Configuration table walks, which return configuration information for the translation context.
  • Translation table walks, that return translation information that is specific to the transaction address.

The TCU contains caches that reduce the number of configuration and translation table walks that are to be performed. Sometimes no walks are required.

When the TBU receives the translation from the TCU, it stores it in its TLBs. If the translation was successful, the TBU uses it to translate the transaction, otherwise it terminates it.

A processor controls the TCU by:

  • Writing commands to a Command queue in memory.
  • Receiving events from an Event queue in memory.
  • Writing to its configuration registers using the programming interface.

See the Arm® System Memory Management Unit Architecture Specification, SMMU architecture version 3.0 and version 3.1 for more information about the following:

  • Translation.
  • How software communicates with the TCU.

This section contains the following subsections:

Was this page helpful? Yes No