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Arm CoreLink MMU-600 System Memory Management Unit Technical Reference Manual : Product revisions

Product revisions

This section describes the differences in functionality between product revisions:

r0p0First release.
r0p0-r0p1The following changes apply to this release:
  • Modified bits in TCU_CTRL.
  • Modified bits in TBU_CTRL.
r0p1-r0p2This release has no functional changes.
r0p2-r1p0The following changes apply to this release:
  • TCU prefetch of translation tables.
  • Access protection for ACE interfaces.
  • TBU direct indexing and MTLB partitioning.
  • Support for Page Request Interface (PRI), as SMMUv3 defines.
  • Other minor features:
    • Change to the behavior of S1HWATTR.
    • TBU option to support 20‑bit StreamIDs.
    • Option to disable cache maintenance operations on a TBU, a sideband channel protection feature.
r1p0-r2p0The following changes apply to this release:
  • Removal of access protection for ACE interfaces.
  • ACE5‑Lite atomic transaction support in TBU and TCU.
  • Support for a higher number of outstanding read and write transactions in the TBU.
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