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Arm CoreLink MMU-600 System Memory Management Unit Technical Reference Manual : TBU TBS interface signals

TBU TBS interface signals

The TBU TBS interface signals are based on the AMBA ACE5-Lite signals.

The following table shows the TBU TBS interface signals.

Table A-12 TBU TBS interface signals

Signal

Direction

Description

aclk

Input

Clock input.

araddr_s

Input

Read address.

arburst_s

Input

Burst type.

arcache_s

Input

Memory type.

ardomain_s

Input

Shareability domain.

aresetn

Input

Active-LOW reset signal.

arid_s

Input

Read address ID.

arlen_s

Input

Burst length.

arlock_s

Input

Lock type.

arprot_s

Input

Protection type.

arqos_s

Input

Quality of Service (QoS).

arready_s

Output

Read address ready.

arregion_s

Input

Region identifier.

arsize_s

Input

Burst size.

armmussid_s

Input

These signals indicate the StreamID, SubstreamID, and ATS translated status of the originating transaction.

These signals are defined by the AXI5 Untranslated_Transactions extension.

armmusid_s

Input

armmussidv_s

Input

armmusecsid_s

Input

armmuatst_s

Input

arvalid_s

Input

Read address valid.

awaddr_s

Input

Write address.

awatop_s

Input

Atomic operation.

awburst_s

Input

Burst type.

awcache_s

Input

Memory type.

awdomain_s

Input

Shareability domain.

awid_s

Input

Write address ID.

awlen_s

Input

Burst length.

awlock_s

Input

Lock type.

awprot_s

Input

Protection type.

awqos_s

Input

QoS.

awready_s

Output

Write address ready.

awregion_s

Input

Region identifier.

awsize_s

Input

Burst size.

awmmussid_s

Input

These signals indicate the StreamID, SubstreamID, and ATS translated status of the originating transaction.

These signals are defined by the AXI5 Untranslated_Transactions extension.

awmmusid_s

awmmussidv_s

awmmusecsid_s

awmmuatst_s

awvalid_s

Input

Write address valid.

bid_s

Output

Response ID.

bready_s

Input

Response ready.

bresp_s

Output

Write response.

bvalid_s

Output

Write response valid.

rdata_s

Output

Read data.

rid_s

Output

Read ID.

rlast_s

Output

Read last.

rready_s

Input

Read ready.

rvalid_s

Output

Read valid.

wdata_s

Input

Write data.

wlast_s

Input

Write last.

wready_s

Output

Write ready.

wstrb_s

Input

Write strobes.

wvalid_s

Input

Write valid.

aruser_s

Input

Read address (AR) channel user signal.

awuser_s

Input

Write address (AW) channel user signal.

wuser_s

Input

Write data (W) channel user signal.

ruser_s

Output

Read data (R) channel user signal.

buser_s

Output

Write response (B) channel user signal.

awakeup_s

Input

Wakeup signal.

arsnoop_s

Input

Transaction type of read transaction.

awsnoop_s[3]

Input

Transaction type of write transaction.

awstashnid_s[10:0]

Input

These signals are defined by the AXI5 Cache_Stash_Transactions extension.

If TBUCFG_STASH = 0, these signals are ignored.

awstashniden_s

Input

awstashlpid_s[4:0]

Input

awstashlpiden_s

Input

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