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Each TCU Node Control register controls how the TCU communicates with a single node. A node is a DTI master that is typically either a TBU or a PCIe Root Complex that implements ATS.

The TCU_NODE_CTRLn characteristics are:

Usage constraints

The DIS_DVM bit can be used for TBU nodes, but is ignored for ATS nodes.

When TCU_SCR.NS_UARCH = 0, Non‑secure accesses to this register are RAZ/WI.

Writes to this register are possible only when both SMMU_CR0.SMMUEN = 0 and SMMU_S_CR0.SMMUEN = 0. Writes at other times are ignored.

After modifying this register, software must issue an INV_ALL operation using the SMMU_S_INIT register, before it sets SMMUEN to 1. Failure to issue an INV_ALL operation results in unpredictable behavior.


The value of the TCUCFG_NUM_TBU configuration parameter defines n, that is, the number of TCU_NODE_CTRL registers that are implemented. Each register has an address width of 4 bytes, therefore the offset of a register n is:

0x09000 + (4 × n)









The following figure shows the bit assignments.

Figure 3-6 TCU_NODE_CTRL register bit assignments

The following table shows the bit assignments.

Table 3-20 TCU_NODE_CTRL register bit assignments

Bits Name Function
[31:5] - Reserved.

Disable DVM. When this bit is set to 1, the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations that are issued over DTI.


This bit is ignored for connected DTI-ATS masters, because they never participate in DVM invalidation.
[3:2] - Reserved.
[1:0] PRI_LEVEL Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before requests from a node with a lower priority level.
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