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TCU_NODE_STATUSn

Each TCU Node Status register provides the status of a DTI master. A node is a DTI master that is typically either a TBU or a PCIe Root Complex that implements ATS.

The TCU_NODE_STATUSn characteristics are:

Usage constraints

This register indicates the status of the corresponding node only when the node is connected.

When TCU_SCR.NS_UARCH = 0, Non-secure accesses to this register are RAZ.

Configurations

The value of the TCUCFG_NUM_TBU configuration parameter defines the number of TCU_NODE_CTRL registers that are implemented. Each register has an address width of 4 bytes, therefore the offset of a register n is:

0x09400 + (4 × n)

Attributes
Offset

0x094000x097FC

Type

RO

Reset

0x00000000

Width

32

The following figure shows the bit assignments.

Figure 3-7 TCU_NODE_STATUS register bit assignments


The following table shows the bit assignments.

Table 3-21 TCU_NODE_STATUS register bit assignments

Bits Name Function

[31:2]

-

Reserved.

[1]

ATS

ATS implemented:

0The corresponding node is a TBU that is connected to the TCU using the DTI‑TBU protocol.
1The corresponding node is a PCIe Root Complex that supports ATS, and is connected to the TCU using the DTI‑ATS protocol.

[0]

CONNECTED

DTI link is connected:

0The DTI link for the corresponding node is not connected.
1The DTI link for the corresponding node is connected.

If a DTI link is not connected, accesses to TBU registers are RAZ/WI. However, the state might change between reading this register and attempting to access the TBU.

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