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About the programmers model

This section provides general information about the MMU-600 register properties.

The following information applies to the MMU-600 registers:

  • The base address is not fixed, and can be different for any particular system implementation. The offset of each register from the base address is fixed.
  • Do not attempt to access reserved or unused address locations. Attempting to access these locations can result in unpredictable behavior.
  • Unless otherwise stated in the accompanying text:

    • Do not modify undefined register bits.

    • Ignore undefined register bits on reads.
    • All register bits are reset to 0 by a system or powerup reset.
  • Access type is described as follows:

    RWRead and write.
    RORead only.
    WOWrite only.
    RAZRead as zero.
    WIWrites ignored.
  • Bit positions that are described as reserved are:

    • In an RW register, RAZ/WI.

    • In an RO register, RAZ.
    • In a WO register, WI.

The MMU-600 registers are accessed using the PROG APB4 slave interface on the TCU, and cannot be accessed directly through any other slave interfaces.

Some registers are 64 bits, but the PROG APB4 interface is 32 bits. Because software accesses 64‑bit registers 32 bits at a time, such accesses are not guaranteed to be 64‑bit atomic. This behavior does not cause problems for software, because the SMMUv3 architecture does not require 64‑bit atomic access to any registers.

The programmers model contains separate TBU and TCU regions for internal control, RAS, and identification registers. Accesses to unmapped or reserved registers are RAZ/WI. Non-secure accesses to Secure registers are RAZ/WI. The MMU-600 implements the identification register scheme that the SMMUv3 architecture defines.

The MMU-600 implements all the Performance Monitor Counter Group (PMCG) registers that the SMMUv3 architecture defines, except for:

  • SMMU_PMCG_IRQ_CFG0.
  • SMMU_PMCG_IRQ_CFG1.
  • SMMU_PMCG_IRQ_CFG2.
  • SMMU_PMCG_IRQ_STATUS.

The MMU-600 does not implement the following SMMUv3 architectural registers, and accesses to these locations are RAZ/WI:

  • SMMU_IDR4.
  • SMMU_STATUSR.
  • SMMU_AGBPA.
  • SMMU_GATOS_*.
  • SMMU_S_IDR4.
  • SMMU_S_AGBPA.
  • SMMU_S_GATOS_*.
  • SMMU_VATOS_*.

See the Arm® System Memory Management Unit Architecture Specification, SMMU architecture version 3.0 and version 3.1 for more information about the SMMU architectural registers.

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