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SMMU architectural registers

The MMU-600 implements many of the SMMU architectural registers, as defined by the Arm® System Memory Management Unit Architecture Specification, SMMU architecture version 3.0 and version 3.1.

The following table lists the SMMUv3 architectural registers that the MMU-600 implements.

Note

All writable register fields reset to 0 unless the SMMU architecture specifies otherwise.

Table 3-1 SMMUv3 architectural registers

Register Name Description

SMMU_S_IDR0 - SMMU_S_IDR3

SMMU Secure feature Identification Registers

Provides information about the Secure features that the SMMU implementation supports.

SMMU_S_CR0

Secure global Control Register 0

Provides global configuration of the Secure SMMU.

SMMU_S_CR0ACK

Secure global Control Register 0 update Acknowledge

Provides acknowledgement of completion of updates to SMMU_S_CR0.

SMMU_S_CR1

SMMU_S_CR2

Secure global Control Registers

Provides the controls for Secure table and queue access attributes.

SMMU_S_INIT

Secure Initialization control register

Provides a control to invalidate all Secure SMMU caching on system initialization.

SMMU_S_GBPA

Secure Global Bypass Attribute register

Controls the global bypass attributes that are used for transactions from Secure streams when the MMU is disabled.

SMMU_S_IRQ_CTRL

Secure Interrupt Control register

Contains enables for SMMU interrupts.

SMMU_S_IRQ_CTRLACK

Secure Interrupt Control register update Acknowledge

Provides acknowledgement of the completion of updates to SMMU_S_IRQ_CTRL.

SMMU_S_GERROR

Secure Global Error status register

Provides information on Secure global programming interface errors.

SMMU_S_GERRORN

Secure Global Error Acknowledgement register

Contains the acknowledgement fields for SMMU_S_GERROR errors.

SMMU_S_GERROR_IRQ_CFG0 - SMMU_S_GERROR_IRQ_CFG2

Secure Global Error IRQ Configuration register

Contains the Secure MSI address configuration for the GERROR IRQ.

SMMU_S_STRTAB_BASE

Secure Stream Table Base address register

Contains the base address and attributes for the Secure Stream table.

SMMU_S_STRTAB_BASE_CFG

Secure Stream Table Base Configuration register

Contains configuration fields for the Secure Stream table.

SMMU_S_CMDQ_BASE

Secure Command queue Base address register

Contains the base address and attributes for the Secure Command queue.

SMMU_S_CMDQ_PROD

Secure Command queue Producer index register

Contains the Secure Command queue index for writes by the producer.

SMMU_S_CMDQ_CONS

Secure Command queue Consumer index register

Contains the Secure Command queue index for reads by the consumer.

SMMU_S_EVENTQ_BASE

Secure Event queue Base address register

Contains the base address and attributes for the Secure Event queue.

SMMU_S_EVENTQ_PROD

Secure Event queue Producer index register

Contains the Secure Event queue index for writes by the producer.

SMMU_S_EVENTQ_CONS

Secure Event queue Consumer index register

Contains the Secure Event queue index for reads by the consumer.

SMMU_S_EVENTQ_IRQ_CFG0 - SMMU_S_EVENTQ_IRQ_CFG2

Secure Event queue IRQ Configuration registers

Contains the MSI address configuration for the Secure Event queue IRQ.

SMMU_IDR0 - SMMU_IDR3

SMMU_IDR5

SMMU feature Identification Registers

Provides information about the features that the SMMU implementation supports.

SMMU_IIDR

Implementation Identification Register

Provides implementer, part, and revision information for the SMMU implementation.

SMMU_AIDR

Architecture Identification Register

Identifies the SMMU architecture version to which the implementation conforms.

SMMU_CR0

Non‑secure global Control Register 0

Provides the controls for the global configuration of the Non‑secure SMMU.

SMMU_CR0ACK

Non‑secure global Control Register 0 update Acknowledge register

Provides acknowledgement of completion of updates to SMMU_CR0.

SMMU_CR1

Non‑secure global Control Register 1

Provides the controls for Non‑secure table and queue access attributes.

SMMU_CR2

Non‑secure global Control Register 2

Provides the controls for the configuration of the global Non‑secure features.

SMMU_GBPA

Non‑secure Global Bypass Attribute register

Controls the global bypass attributes that are used for transactions from Non‑secure streams when the MMU is disabled.

SMMU_IRQ_CTRL

Non‑secure Interrupt Control register

Provides IRQ enable flags for edge‑triggered wired outputs, if implemented, and MSI writes, if implemented.

SMMU_IRQ_CTRLACK

Non‑secure Interrupt Control register update Acknowledge register

Provides acknowledgement of the completion of updates to SMMU_IRQ_CTRL.

SMMU_GERROR

Non‑secure Global Error status register

Provides information about Non-secure global programming interface errors.

SMMU_GERRORN

Non‑secure Global Error acknowledgement register

Contains the acknowledgement fields for SMMU_GERROR errors.

SMMU_GERROR_IRQ_CFG0

Non‑secure Global Error IRQ Configuration register 0

Contains the MSI address configuration for the GERROR IRQ.

SMMU_GERROR_IRQ_CFG1

Non‑secure Global Error IRQ Configuration register 1

Contains the MSI payload configuration for the GERROR IRQ.

SMMU_GERROR_IRQ_CFG2

Non‑secure Global Error IRQ Configuration register 2

Contains the MSI attribute configuration for the GERROR IRQ.

SMMU_STRTAB_BASE

Non‑secure Stream Table Base address register

Contains the base address and attributes for the Non-secure Stream table.

SMMU_STRTAB_BASE_CFG

Non‑secure Stream Table Configuration register

Contains configuration fields for the Non‑secure Stream table.

SMMU_CMDQ_BASE

Non‑secure Command queue Base address register

Contains the base address and attributes for the Non‑secure Command queue.

SMMU_CMDQ_PROD

Non‑secure Command queue Producer index register

Contains the Non‑secure Command queue index for writes by the producer.

SMMU_CMDQ_CONS

Non‑secure Command queue Consumer index register

Contains the Non‑secure Command queue index for reads by the consumer.

SMMU_EVENTQ_BASE

Non‑secure Event queue Base address register

Contains the base address and attributes for the Non‑secure Event queue.

SMMU_EVENTQ_PROD

Non‑secure Event queue Producer index register

Contains the Non‑secure Event queue index for writes by the producer.

SMMU_EVENTQ_CONS

Non‑secure Event queue Consumer index register

Contains the Non‑secure Event queue index for reads by the consumer.

SMMU_EVENTQ_IRQ_CFG0

Non‑secure Event queue IRQ Configuration register 0

Contains the MSI address configuration for the Event queue IRQ.

SMMU_EVENTQ_IRQ_CFG1

Non‑secure Event queue IRQ Configuration register 1

Contains the MSI payload configuration for the Event queue IRQ.

SMMU_EVENTQ_IRQ_CFG2

Non‑secure Event queue IRQ Configuration register 2

Contains the MSI attribute configuration for the Event queue IRQ.

SMMU_PRIQ_BASE

Non‑secure PRI queue Base address register

Contains the base address and attributes for the Non‑secure PRI queue.

SMMU_PRIQ_PROD

Non‑secure PRI queue Producer index register

Contains the Non‑secure PRI queue index for writes by the producer.

SMMU_PRIQ_CONS

Non‑secure PRI queue Consumer index register

Contains the Non‑secure PRI queue index for reads by the consumer.

SMMU_PRIQ_IRQ_CFG0

Non‑secure PRI queue IRQ Configuration register 0

Contains the MSI address configuration for the PRI queue IRQ.

SMMU_PRIQ_IRQ_CFG1

Non‑secure PRI queue IRQ Configuration register 1

Contains the MSI payload configuration for the PRI queue IRQ.

SMMU_PRIQ_IRQ_CFG2

Non‑secure PRI queue IRQ Configuration register 2

Contains the MSI attribute configuration for the PRI queue IRQ.

The MMU-600 implements an SMMUv3 Performance Monitor Counter Group (PMCG) in the TCU and in each TBU. The following table lists the registers that the MMU-600 implements in each PMCG.

Table 3-2 SMMUv3 PMCG registers

Register Name Description

SMMU_PMCG_EVCNTR0 - SMMU_PMCG_EVCNTR3

SMMU PMCG Event Counter registers

Contains the values of the event counters.

SMMU_PMCG_EVTYPER0 - SMMU_PMCG_EVTYPER3

SMMU PMCG Event Type configuration registers

Configures the events that the corresponding counter counts.

SMMU_PMCG_SVR0 - SMMU_PMCG_SVR3

SMMU PMCG Shadow Value Registers

Contains the shadow value of the corresponding event counter.

SMMU_PMCG_SMR0

SMMU PMCG Stream Match filter Register

Configures the stream match filter for the corresponding event counter.

SMMU_PMCG_CNTENSET0

SMMU PMCG Counter Enable Set register

Provides the set mechanism for the counter enables.

SMMU_PMCG_CNTENCLR0

SMMU PMCG Counter Enable Clear register

Provides the clear mechanism for the counter enables.

SMMU_PMCG_INTENSET0

SMMU PMCG Interrupt contribution Enable Set register

Provides the set mechanism for the counter interrupt contribution enables.

SMMU_PMCG_INTENCLR0

SMMU PMCG Interrupt contribution Enable Clear register

Provides the clear mechanism for the counter interrupt enables.

SMMU_PMCG_OVSCLR0

SMMU PMCG Overflow Status Clear register

Provides the clear mechanism for the overflow status bits and provides read access to the overflow status bit values.

SMMU_PMCG_OVSSET0

SMMU PMCG Overflow Status Set register

Provides the set mechanism for the overflow status bits and provides read access to the overflow status bit values.

SMMU_PMCG_CAPR

SMMU PMCG Counter shadow value Capture Register

Controls the counter shadow value capture mechanism.

SMMU_PMCG_SCR

SMMU PMCG Secure Control Register

Secure Control Register.

SMMU_PMCG_CFGR

SMMU PMCG Configuration information Register

Provides information about the PMCG implementation.

SMMU_PMCG_CR

SMMU PMCG Control Register

Contains the Performance Monitor control flags.

SMMU_PMCG_CEID0 - SMMU_PMCG_CEID1

SMMU PMCG Common Event ID registers

Contains the lower and upper 64 bits of the Common Event identification bitmap.

SMMU_PMCG_IRQ_CTRL

SMMU PMCG IRQ enable register

Contains the Performance Monitors IRQ enable.

SMMU_PMCG_IRQ_CTRLACK

SMMU PMCG IRQ enable Acknowledge register

Provides acknowledgement of the completion of updates to SMMU_PMCG_IRQ_CTRL.

SMMU_PMCG_AIDR

SMMU PMCG Architecture Identification Register

Provides the Performance Monitor Architecture Identification.

SMMU_PMCG_ID_REGS

ID registers

implementation defined.

SMMU_PMCG_PMAUTHSTATUS

PMU Authentication Status register

Performance Monitor authentication status.

SMMU_PMCG_PMDEVARCH

PMU Device Architecture register

Performance Monitor architecture identifier.

SMMU_PMCG_PMDEVTYPE

PMU Device Type register

Performance Monitor device type.

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