TBU_ERRSTATUS
Use the TBU Error Record Primary Syndrome register to find out whether different types of error have occurred on the TBU.
The TBU_ERRSTATUS characteristics are:
- Usage constraints
When TBU_SCR.NS_RAS = 0, Non-secure accesses to this register are RAZ/WI. To prevent race conditions, under certain circumstances, writes to some bits in this register are ignored. Typically, these writes are ignored when software has not yet observed a new error.
- Configurations
This register exists in all MMU-600 configurations. An instance of this register exists for each implemented TBU.
- Attributes
-
Offset 0x08E90Type RW
Reset 0x00000000Width 32
The following figure shows the bit assignments.
Figure 3-16 TBU_ERRSTATUS register bit assignments
The following table shows the bit assignments.
Table 3-32 TBU_ERRSTATUS register bit assignments
| Bits | Name | Function | ||||||
|---|---|---|---|---|---|---|---|---|
| [31] | - | Reserved. | ||||||
| [30] | V |
Register valid. This bit is set to 1 to indicate that at least one RAS error was recorded. Clear this bit by writing a 1 to it. If CE is not |
||||||
| [29:28] | - | Reserved. | ||||||
| [27] | OF |
Overflow. This bit is set to 1 to indicate that multiple correctable errors were
recorded. That is, at least one correctable error was recorded when CE != Clear this bit by writing a 1 to it. A write of 0 is ignored. |
||||||
| [26] | - | Reserved. | ||||||
| [25:24] | CE | Correctable Error. This field is set to 0b10 to indicate that a corrected error occurred.
Clear this field by writing 0b11
to it. If OF is set to 1 and is not being cleared, the write is ignored. A write of
any value other than 0b11 is
ignored. |
||||||
| [23:8] | - | Reserved. | ||||||
| [7:0] | SERR |
Error code. This field provides information about the earliest unacknowledged correctable error, as follows:
Writes to this field are ignored. |