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TCU_SCR

The TCU Secure Control register controls whether Non‑secure software is permitted to access each TCU register group.

The TCU_SCR characteristics are:

Usage constraints

Non‑secure accesses to this register are RAZ/WI.

This register does not control Secure access to the MMU-600 PMU registers. To control Secure PMU register access, use the SMMU_PMCG_SCR register.

Configurations

This register exists in all TCU configurations.

Attributes
Offset

0x08E18

Type

RW

Reset

See register bit assignments.

Width

32

The following figure shows the bit assignments.

Figure 3-5 TCU_SCR register bit assignments


The following table shows the bit assignments.

Table 3-19 TCU_SCR register bit assignments

Bits Name Function

[31:4]

-

Reserved.

[3]

NS_INIT

Non‑secure register access to SMMU_S_INIT. When this bit is set to 0, Non‑secure accesses to the SMMU_S_INIT register are RAZ/WI.

The sec_override input signal defines the reset value of this bit.

[2]

-

Reserved.

[1]

NS_RAS

Non‑secure register access is permitted for RAS registers. When this bit is set to 0, Non‑secure accesses to register addresses 0x08E80-0x08EC0 are RAZ/WI.

The sec_override input signal defines the reset value of this bit.

[0]

NS_UARCH

Non‑secure register access is permitted for MMU-600 registers. When this bit is set to 0, Non‑secure accesses to register addresses 0x08E00-0x08E7C and 0x09000-0x093FC are RAZ/WI.

The sec_override input signal defines the reset value of this bit.

If your implementation might use Secure translation, Arm recommends setting this bit to 0.

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