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TCU_ERRGEN

Use the TCU Error Generation Register to generate tag parity errors, for example when testing error-handling software.

The TCU_ERRGEN characteristics are:

Usage constraints

When TCU_SCR.NS_RAS = 0, Non-secure accesses to this register are RAZ/WI.

Configurations

This register exists in all TCU configurations.

Attributes
Offset

0x08EC0

Type

RW

Reset

0x00000000

Width

64

The following figure shows the bit assignments.

Figure 3-11 TCU_ERRGEN register bit assignments


The following table shows the bit assignments.

Table 3-25 TCU_ERRGEN register bit assignments

Bits Name Function
[63:4] - Reserved.
[3] TCC

Configuration cache tag parity error:

0No tag parity error is written to the configuration cache.
1Entries that are written to the configuration cache include a tag parity error. A fault occurs when the entry is used.
[2] DCC

Configuration cache data parity error:

0No data parity error is written to the configuration cache.
1Entries that are written to the configuration cache include a data parity error. A fault occurs when the entry is used.

Note

Tag parity errors mask data parity errors. When testing data parity error functionality, ensure that software does not set this bit and the TCC bit at the same time.
[1] TWC

Walk cache tag parity error:

0No tag parity error is written to the walk cache.
1Entries that are written to the walk cache include a tag parity error. A fault occurs when the entry is used.
[0] DWC

Walk cache data parity error:

0No data parity error is written to the walk cache.
1Entries that are written to the walk cache include a data parity error. A fault occurs when the entry is used.

Note

Tag parity errors mask data parity errors. When testing data parity error functionality, ensure that software does not set this bit and the TWC bit at the same time.
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