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Distributor ACE-Lite slave interface

The ACE-Lite slave port on the GIC-600 Distributor provides access to the entire register map except for the GITS_TRANSLATER registers. The interface supports either 64-bit, 128-bit, or 256-bit data widths.

The GIC-600 only accepts single beat accesses of the sizes for each register that are shown in the Programmers model, see Chapter 4 Programmers model. All other accesses are rejected and given either an OK or SLVERR response that is based on the GICT_ERR0CTLR.UE bit.

When the GIC-600 is a monolithic configuration, the Distributor and ITS both share an ACE-Lite slave port, and the DeviceID for the ITS translation is taken from awuser_s[DEVICE_ID_WIDTH+2:3]. See 2.3 ITS, for more information about the ITS.


The a<x>user_s[2:0] signals are not used and must be tied to 0.

Table 2-3 Acceptance capabilities

Attribute Capability
Combined acceptance capability 3
Read acceptance capability 2
Read data reorder depth 1
Write acceptance capability 2

The GIC-600 uses a<x>cache_s, a<x>domain_s, and a<x>bar_s signals to detect cache maintenance operations and barrier transactions that are responded to in a protocol-compliant manner but are otherwise ignored. The GIC-600 also ignores other cachability, shareability, and protection settings except Security, a<x>prot_s[1].

If you are connecting to an AXI3 or AXI4 port, signals a<x>domain>_s, a<x>bar_s and, for AXI3, a<x>len[7:4] must all be tied to 0.

The GIC-600 has a separate awakeup_s signal to force the GIC to wakeup when it is hierarchically clock-gated through the Q-Channel. The awakeup_s signal must be connected to a cleanly registered version of (awvalid_s | arvalid_s) to ensure that the GIC does not request to be woken up due to incoming signal glitches.

The GIC-600 address map can have several pages. The number of pages depends on your configuration. See 4.1.1 Register map pages.

You must set up the system address map so that each core accesses the GICD page on its local chip at the same address. All other pages must be globally accessible, although access of pages on a remote chip by a core is expected to be rare.

In most configurations, the GIC-600 ignores address bits above ceiling (log2(page_count)) + 15. For example, a configuration that uses 11 pages ignores address bits above 19, and any address bits of the form 0xXXXXX00000 is accepted to access the GICD page of the memory map. However, in monolithic configurations, where the Distributor and ITS share the ACE-Lite slave port, there are two address tie-offs that specify the full page address of the GICD and GITS_TRANSLATER pages. The page address comprises address bits[x:16]. For example, if the GICD page is at 32-bit address 0xFFFF0000, the tie-off is 16-bit 0xFFFF. See 2.1.5 Distributor miscellaneous signals for information about the Distributor miscellaneous signals.