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Interconnect

The GIC-600 uses AXI4-Stream interfaces for communication between some blocks.

These blocks are:

  • Distributor to and from ITS.
  • Distributor to and from Redistributors.
  • Distributor to Distributor for cross-chip communications.
  • Distributor to and from the SPI Collator.
  • Distributor to and from the Wake Request block.

All these interfaces use fully credited schemes where all messages are guaranteed to be accepted without dependency on any other port.

Apart from the cross-chip communications, GIC-600 provides an AXI4-Stream interconnect for transporting messages. However, messages can be sent over an existing interconnect provided the interconnect is free-flowing.

The key requirements of the interconnect are as follows:

  • The Distributor must appear at the same address on each chip. This is to maintain the view of a single Distributor across the system.
  • Free-flowing access from the ITS and Distributor to memory.
  • All AXI4-Stream messages must be free-flowing.
  • Accesses to GITS_TRANSLATER at the ITS must occur at the correct offsets, that is, the subsequent 64K page to the related ITS control registers.

This section contains the following subsection:

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