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The ITS provides a software mechanism for translating message-based interrupts into LPIs. The ITS is supported optionally in configurations that support LPIs.

A peripheral generates an LPI by writing to the GITS_TRANSLATER in the ITS. The write provides the ITS with the following information:

  • EventID (VID). A value written to GITS_TRANSLATER. The EventID identifies which interrupt the peripheral is sending. Each interrupt source is identified by an Interrupt Identifier (INTID). The EventID might be the same as the INTID, or it might be translated by the ITS into the INTID.
  • DeviceID (DID). The DeviceID is a unique identifier that identifies the peripheral.

The following figure shows the ITS block.

Figure 2-3 ITS block

The ITS is an implementation of the GICv3 Interrupt Translation Service as described in the ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0. The ITS translates MSI requests to the required LPI and target. It also has a set of commands for managing LPIs for core power management.

A main use of the ITS is the translation of MSI/MSIx messages from a PCIe Root Complex (RC). To complete the translation, the ITS must be supplied with a DeviceID that is derived from the PCIe RequestorID. To reduce the distance that the DeviceID is transferred and to enable better compartmentalization between RCs, the ITS is best placed next to the RC. To ease integration, the ITS has an optional bypass switch as shown in the ITS block diagram. If the bypass switch is not configured, the ACE_Lite slave and master ports connect to the ITS directly. See 2.3.1 ITS ACE-Lite slave interface and 2.3.2 ITS ACE-Lite master interface.

See 3.2.9 Interrupt translation service (ITS) for more information.

The following figure provides an example of the ITS integration process.

Figure 2-4 ITS integration

An ITS can be placed anywhere in the system so that it is seen by devices that want to send MSIs. However, the system is responsible for ensuring that the DeviceID reaching each ITS is not spoofed by rogue software using either a<x>user signals or MSI-64. See 2.4 MSI-64 Encapsulator.

If the ITS is placed downstream of an ACE interconnect, care must be taken to avoid system deadlock. See Chapter 3, Key integration points of the ARM® CoreLink™ GIC‑600 Generic Interrupt Controller Configuration and Integration Manual.

See 3.2.9 Interrupt translation service (ITS) for more information about each inner block.

This section contains the following subsections:

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