ITS ACE-Lite master interface
The ITS AMBA® AXI4 ACE-Lite master interface has a configurable width of 64 bits, 128 bits, or 256 bits. If the bypass switch is not included, the ID width is 4 bits. If the bypass switch is included, the ID width is one more than the ID width of the corresponding input channel. The slave, master, and address data widths must match.
The ACE-Lite master port issues accesses to the ITS private tables and Command queue. If the bypass switch is configured, the port also forwards transactions from the slave interface. The ACE-Lite bus can issue I/O coherent transactions, therefore you can place these tables in shared memory if required.
- When heavily loaded, the ITS creates a necessary dependency between writes on its slave port and reads on its master port. You must ensure that any writes that back up to the slave port do not prevent the free-flow of both reads and writes to the memory.
- In an ACE system, you must ensure that the write channel from any core cache that could be snooped is not blocked by accesses to the ITS slave port. If the write channel is blocked, and the snoop is prevented from completing its task, a potential deadlock can result.
ARM strongly recommends that if you place the ITS downstream of an ACE interconnect, then you must not place tables in shareable memory.
If the bypass switch is included, apart from transactions that are forwarded from the slave port, the ITS can issue the following transaction types:
- 256-bit aligned read to the Command queue.
- 64-bit aligned read and write to the Device table.
- 32-bit aligned read and write to the Interrupt Translation Table (ITT).
- 16-bit aligned read and write to the Collection table.
ITS issued transactions output the DeviceID on the a<x>user_ signals. The DeviceID is used for information and does not have to be routed anywhere if it is not required. If the bypass switch is included, ITS issued transactions are identified by a value of 0 on the top bit of the a<x>id.