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About the GIC-600

The GIC-600 is a generic interrupt controller that handles interrupts from peripherals to the cores and between cores. The GIC-600 supports a distributed microarchitecture containing several individual blocks that are used to provide a flexible GIC implementation.

The GIC-600 supports the GICv3 architecture, see ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0.

The microarchitecture scales from a single core to coherent, unified, and consistent, multichip environments containing up to 16 chips of up to 512 cores each.


This manual defines a chip as a SoC that is integrated with the GIC-600. A single-chip system has one SoC. A multichip system can have several SoCs that are connected externally, or a SoC comprising several SoCs connected inside a single physical package. In all cases, each SoC is integrated with the GIC-600.

All the GIC-600 blocks communicate through fully credited AXI4-Stream interface channels. Channels can be routed over dedicated AXI4-Stream buses, or over any available free-flowing transport layer in the system. A channel is described as free-flowing if all transactions on that channel complete without a non-transient dependency on any other transaction.

The GIC-600 includes build scripts that can create appropriate levels of hierarchy for any particular configuration. In small configurations, the distribution can be hidden and internally optimized.


The microarchitecture for product versions r0p0, r0p1, and r0p2 is limited to a maximum of 16 cores on a single chip.