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Features

The GIC-600 provides interrupt services and masking, registers and programming, interrupt grouping, security, performance monitoring, and error correction.

Interrupt services and masking:

  • Support for the following interrupt types:
    • Up to 56000 LPIs. A peripheral generates these interrupts by writing to a memory-mapped register in the GIC-600. See  Distributor configuration.
    • Up to 960 SPIs in groups of 32. See  Distributor configuration.
    • Up to 16 PPIs that are independent for each core and can be programmed to support either edge-triggered or level-sensitive interrupts. See  Redistributor configuration.
    • Up to 16 SGIs that are generated through the GIC CPU interface of a core.
  • Up to 16 ITS modules that provide device isolation and ID translation for message-based interrupts and enable virtual machines to program devices directly.
  • Interrupt masking and prioritization with 32 priority levels, five bits per interrupt.

Registers and programming:

  • Flexible affinity routing, using the Multiprocessor Identification Register (MPIDR) addresses, including support for all four affinity levels.
  • Single ACE-Lite slave port on each chip for programming of all GIC Distributor (GICD) registers, GIC Interrupt Translation Service (GITS) registers, and GIC Redistributor (GICR) registers. Each ITS has an optional ACE-Lite slave port for programming the GITS_TRANSLATER register.
  • Coherent view of SPI register data across multiple chips.

Security:

  • A global Disable Security (DS) bit. This bit enables support for systems without security.
  • The following interrupt groups allow interrupts to target different Exception levels:

    • Group 0.
    • Non-secure Group 1.
    • Secure Group 1.

    See  Security for more information about security and groupings.

Note

For more information about Exception levels, see the Arm® Architecture Reference Manual ARMv8, for ARMv8‑A architecture profile.

Performance monitoring:

  • Performance Monitoring Unit (PMU) counters with snapshot functionality.

Error correction:

  • ARMv8.2 Reliability Accessibility Serviceability (RAS) architecture-compliant error reporting for:

    • Software access errors.
    • ITS command and translation errors.
    • Error Correcting Code (ECC) errors.