Interrupt Configuration Register, GICP_IRQCR
This register controls the counter interrupts.
The GICP_IRQCR characteristics are:
- Usage constraints
- There are no usage constraints.
- Available in all GIC-600 configurations.
- See GICP register summary.
The following figure shows the bit assignments.
Figure 4-56 GICP_IRQCR bit assignments
The following table shows the bit assignments.
Table 4-72 GICP_IRQCR bit assignments
Returns 0 if an invalid entry is written.
Creates a level-triggered interrupt if it is owned on chip. Otherwise it behaves as a normal message-based SPI.