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Arm CoreLink GIC-600 Generic Interrupt Controller Technical Reference Manual : ECC error reporting and recovery

ECC error reporting and recovery

When an ECC error is detected, the GIC-600 attempts to contain the error and ensure it cannot propagate further.

The following table shows the GIC behavior when errors are detected in each RAM.

Table 3-6 ECC error reporting

RAM Action in response to an Uncorrectable Error
ITS caches All ITS caches are memory that is backed. The contents are reloaded from memory. However, if entries are locked in the errored cache line, the lock is lost. Software can use the GITS_OPSR register to determine if all expected locked entries are still in place.
SPI The SPI is flagged as being in error and the error is reported through the GICD_IERRRn register. The corrupted RAM contents can be read until the error is cleared by writing GICD_IERRRn. SPIs that are in the error state can also be determined by reading the GICD_IERRRn register. This SPI is not reused until it is reprogrammed and re-enabled.

All information from the RAM entry is reported. Software can determine the set of interrupts that might have errors, based on the reported ID, to check priority, and to target information.


Repeated double errors in the LPI cache cause an overflow of the error record, which means subsequent information is lost. Arm recommends that a high priority SPI is used to trigger a core to clear the error record as fast as possible.
Redistributor RAM

In the Redistributor, only group and priority are maintained in the RAM. If an error occurs, this information becomes unknown for four interrupts. Pending and Active states are maintained but the enable is cleared so that the interrupt is not forwarded.

You can determine the interrupts that are in error by reading the GICR_IERRVR register.


Because the group is unknown, it is assumed to be Secure, and therefore interrupt deactivates can be ignored. Software must consider this as part of the recovery sequence.

It is also possible for a GenerateSGI packet to become corrupted. In this case, the GenerateSGI is reported as bad.

For more information about Pending and Active PPI states, see the Arm® GICv3 and GICv4 Software Overview.

SGI The SGI RAM holds group and Non-Secure Access Control (NSACR) information for all cores. It is used to enable wakeup of the Redistributor as required. If an error occurs in the RAM, then all SGIs for that core are considered to be Secure. This prevents Non-secure masters from raising Secure interrupts incorrectly.
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