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Arm CoreLink GIC-600 Generic Interrupt Controller Technical Reference Manual : ACE interface signals

ACE interface signals

The following table shows the GIC-600 ACE signal set.

Table A-5 ACE interface signals

Signal name Type Description
Write address channel signals → Slave
There are multiple versions of this bus. Buses that have _its[_<num>] are dedicated ITS slave ports for GITS_TRANSLATER only. There is always one port that has no _its suffix that is used for all registers except GITS_TRANSLATER. This port is used for all registers in monolithic configurations.
awuser_[its[_<num>]]_s[variable:0]a Input

Optional user-defined signal in the write address channel. Supported only in AXI4.

Indicates the DeviceID of writes to GITS_TRANSLATER if MSI_64 is not configured.

awatop_[its[_<num>]]_s[5:0] Input

This signal is only present on ITSs with atomic support. It indicates the type of access being received by the slave

awatop_[its[_<num>]]_m[5:0] Input This signal is only present on ITSs with atomic support. It indicates the type of access being forwarded by the master port. Atomic accesses are never generated by an ITS and are only forwarded from the slave port.
awaddr_[its[_<num>]]_s[variable:0]a Input The write address gives the address of the first transfer in a write burst transaction.
awid_[its[_<num>]]_s[variable:0]a Input This signal is the identification tag for the write address group of signals.
awlen_[its[_<num>]]_s[7:0] Input The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
awsize_[its[_<num>]]_s[2:0] Input This signal indicates the size of each transfer in the burst.
awburst_[its[_<num>]]_s[1:0] Input The burst type and the size information, determine how the address for each transfer within the burst is calculated.
awprot_[its[_<num>]]_s[2:0] Input This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.
awvalid_[its[_<num>]]_s Input This signal indicates that the channel is signaling valid write address and control information.
awready_[its[_<num>]]_s Output This signal indicates that the slave is ready to accept an address and associated control signals.
awcache_[its[_<num>]]_s[3:0] Input This signal indicates how transactions are required to progress through a system.
awdomain_[its[_<num>]]_s[1:0] Input This signal indicates the shareability domain of a write transaction.
awsnoop_[its[_<num>]]_s[2:0] Input This signal indicates the transaction type for Shareable write transactions.
awbar_[its[_<num>]]_s[1:0] Input This signal indicates a write barrier transaction.
Write data channel signals → Slave
wstrb_[its[_<num>]]_s[variable:0]a Input This signal indicates which byte lanes hold valid data. There is one write strobe bit for every eight bits of the write data bus.
wdata_[its[_<num>]]_s[variable:0]a Input Write data.
wvalid_[its[_<num>]]_s Input This signal indicates that valid write data and strobes are available.
wready_[its[_<num>]]_s Output This signal indicates that the slave can accept the write data.
wlast_[its[_<num>]]_s Input This signal indicates the last transfer in a write burst.
Write response channel signals → Slave
bid_[its[_<num>]]_s[variable:0]a Output This signal is the ID tag of the write response.
bvalid_[its[_<num>]]_s Output This signal indicates that the channel is signaling a valid write response.
bready_[its[_<num>]]_s Input This signal indicates that the master can accept a write response.
bresp_[its[_<num>]]_s[1:0] Output This signal indicates the status of the write transaction.
Read address channel signals → Slave
arcache_[its[_<num>]]_s[3:0] Input This signal indicates how transactions are required to progress through a system.
arbar_[its[_<num>]]_s[1:0] Input This signal indicates a read barrier transaction.
arsnoop_[its[_<num>]]_s[3:0] Input This signal indicates the transaction type for Shareable read transactions.
ardomain_[its[_<num>]]_s[1:0] Input This signal indicates the shareability domain of a read transaction.
araddr_[its[_<num>]]_s[variable:0]a Input The read address gives the address of the first transfer in a read burst transaction.
arid_[its[_<num>]]_s[variable:0]a Input This signal is the identification tag for the read address group of signals.
arlen_[its[_<num>]]_s[7:0] Input This signal indicates the exact number of transfers in a burst. This changes between AXI3 and AXI4.
arsize_[its[_<num>]]_s[2:0] Input This signal indicates the size of each transfer in the burst.
aruser_[its[_<num>]]_s[2:0] Input

This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or instruction access.

arburst_[its[_<num>]]_s[1:0] Input The burst type and the size information determine how the address for each transfer within the burst is calculated.
arprot_[its[_<num>]]_s[2:0] Input This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.
arvalid_[its[_<num>]]_s Input This signal indicates that the channel is signaling valid read address and control information.
arready_[its[_<num>]]_s Output This signal indicates that the slave is ready to accept an address and associated control signals.
Read data channel signals → Slave
rid_[its[_<num>]]_s[variable:0]a Output This signal is the identification tag for the read data group of signals generated by the slave.
rdata_[its[_<num>]]_s[variable:0]a Output Read data.
rresp_[its[_<num>]]_s[1:0] Output This signal indicates the status of the read transfer.
rlast_[its[_<num>]]_s Output This signal indicates the last transfer in a read burst.
rvalid_[its[_<num>]]_s Output This signal indicates that the channel is signaling the required read data.
rready_[its[_<num>]]_s Input This signal indicates that the master can accept the read data and response information.
Write address channel signals → Master. Only present if LPI support is configured.
Buses containing _its[_<num>] are used by the specific ITS for read/writes to the private tables and Command queue. Buses without an _its suffix are used for accesses to the LPI Pending and Property tables. This port performs all accesses in monolithic configurations.
awaddr_[its[_<num>]]_m[variable:0]a Output The write address gives the address of the first transfer in a write burst transaction.
awid_[its[_<num>]]_m[variable:0]a Output This signal is the identification tag for the write address group of signals.
awlen_[its[_<num>]]_m[7:0] Output The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
awsize_[its[_<num>]]_m[2:0] Output This signal indicates the size of each transfer in the burst.
awburst_[its[_<num>]]_m[1:0] Output The burst type and size information determine how the address for each transfer within the burst is calculated.
awprot_[its[_<num>]]_m[2:0] Output This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.
awvalid_[its[_<num>]]_m Output This signal indicates that the channel is signaling valid write address and control information.
awready_[its[_<num>]]_m Input This signal indicates that the channel is signaling valid write address and control information.
awcache_[its[_<num>]]_m[3:0] Output This signal indicates how transactions are required to progress through a system.
awdomain_[its[_<num>]]_m[1:0] Output This signal indicates the shareability domain of a write transaction.
awsnoop_[its[_<num>]]_m[2:0] Output This signal indicates the transaction type for Shareable write transactions.
awbar_[its[_<num>]]_m[1:0] Output This signal indicates a write barrier transaction.
awuser_m[variable:0]a Output Optional user-defined signal in the write address channel.
Write data channel signals → Master. Only present if LPI support is configured.
wstrb_[its[_<num>]]_m[variable:0]a Output This signal indicates which byte lanes hold valid data. There is one write strobe bit for every eight bits of the write data bus.
wdata_[its[_<num>]]_m[variable:0]a Output Write data.
wvalid_[its[_<num>]]_m Output This signal indicates that valid write data and strobes are available.
wready_[its[_<num>]]_m Input This signal indicates that the slave can accept the write data.
wlast_[its[_<num>]]_m Output This signal indicates the last transfer in a write burst.
Write response channel signals → Master. Only present if LPI support is configured.
bid_[its[_<num>]]_m[variable:0]a Input This signal is the ID tag of the write response.
bvalid_[its[_<num>]]_m Input This signal indicates that valid write data and strobes are available.
bready_[its[_<num>]]_m Output This signal indicates that the channel is signaling a valid write response.
bresp_[its[_<num>]]_m[1:0] Input This signal indicates the status of the write transaction.
Read address channel signals → Master. Only present if LPI support is configured.
araddr_[its[_<num>]]_m[variable:0]a Output The read address gives the address of the first transfer in a read burst transaction.
arid_[its[_<num>]]_m[variable:0]a Output This signal is the identification tag for the read address group of signals.
arlen_[its[_<num>]]_m[7:0] Output This signal indicates the exact number of transfers in a burst. This changes between AXI3 and AXI4.
arsize_[its[_<num>]]_m[2:0] Output This signal indicates the size of each transfer in the burst.
arburst_[its[_<num>]]_m[1:0] Input The burst type and the size information determine how the address for each transfer within the burst is calculated.
arprot_[its[_<num>]]_m[2:0] Output This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.
arvalid_[its[_<num>]]_m Output The signal indicates that the channel is signaling valid read address and control information.
arready_[its[_<num>]]_m Input This signal indicates that the slave is ready to accept an address and associated control signals.
arcache_[its[_<num>]]_m[3:0] Output This signal indicates how transactions are required to progress through a system.
ardomain_[its[_<num>]]_m[1:0] Output This signal indicates the shareability domain of a read transaction.
arsnoop_[its[_<num>]]_m[3:0] Output This signal indicates the transaction type for Shareable read transactions.
arbar_[its[_<num>]]_m[1:0] Output This signal indicates a read barrier transaction.
aruser_[its[_<num>]]_m[variable:0]a Output Optional user-defined signal in the read address channel. Supported only in AXI4.
Read data channel signals → Master. Only present if LPI support is configured.
rid_[its[_<num>]]_m[variable:0]a Input This signal is the identification tag for the read data group of signals generated by the slave.
rada_[its[_<num>]]_m[variable:0]a Input Read data.
rresp_[its[_<num>]]_m[1:0] Input This signal indicates the status of the read transfer.
rlast_[its[_<num>]]_m Input This signal indicates the last transfer in a read burst.
rvalid_[its[_<num>]]_m Input This signal indicates that the channel is signaling the required read data.
rready_[its[_<num>]]_m Output This signal indicates that the master can accept the read data and response information.
a The variable is configuration-dependent.
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