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Arm CoreLink GIC-600 Generic Interrupt Controller Technical Reference Manual : Interblock signals

Interblock signals

The following table shows the GIC-600 interblock signals.

Table A-7 Interblock signals

Signal name Forward or reverse Source or destination Description
icdptready Reverse Redistributor → Distributor AXI4-Stream compliant bus for communication between the Distributor and a Redistributor. It is fully credited and must never backpressure. It can be sent over any free-flowing interconnect.
icdptvalid Forward Distributor → Redistributor

icdptdata[variable:0]a

Forward
icdptlast Forward
icdptwakeup Forward Registered wake signal to indicate that a message is arriving or is about to arrive on the icdp bus. Signals icdptvalid and icdptready control data transfer.
icdptdest Forward

Specifies the destination Redistributor block.

This signal is only present on the Distributor.

See AXI4-Stream interfaces in Functional integration guidelines of the Arm®CoreLink™ GIC‑600 Generic Interrupt Controller Configuration and Integration Manual for more information.

icdptkeep Forward

Indicates the data bytes that must be transferred.

This signal is only present on the Distributor.

icpdtready Reverse AXI4-Stream compliant bus for communication between the Redistributor and the Distributor. It is fully credited and can be sent over any free-flowing interconnect.
icpdtvalid Forward Redistributor → Distributor

icpdtdata[variable:0]a

Forward
icpdtlast Forward
icpdtwakeup Forward Registered wake signal to indicate that a message is arriving or is about to arrive on the icpd bus. Signals icpdtvalid and icpdtready control data transfer.
icpdtid Forward

Specifies the source Redistributor block.

This signal is only present on the Distributor.

See AXI4-Stream interfaces in Functional integration guidelines of the Arm®CoreLink™ GIC‑600 Generic Interrupt Controller Configuration and Integration Manual for more information.

icpdtkeep Forward

Indicates the data bytes that must be transferred.

This signal is only present on the Redistributor.

icditready Reverse ITS → Distributor AXI4-Stream compliant bus for communication from the Distributor to the ITS. It is fully credited and can be sent over any free-flowing interconnect.
icditvalid Forward Distributor → ITS

icditdata[variable:0]a

Forward
icditlast Forward
icditwakeup Forward Indicates that a message is arriving or is about to arrive on the icdi bus. Signals icditvalid and icditready control data transfer.
icditdest Forward

Specifies the destination ITS block.

This signal is only present on the Distributor.

See AXI4-Stream interfaces in Functional integration guidelines of the Arm®CoreLink™ GIC‑600 Generic Interrupt Controller Configuration and Integration Manual for more information.

icditkeep Forward

Indicates the data bytes that must be transferred.

This signal is only present on the Distributor.

icidtready Reverse AXI4-Stream compliant bus for communication from the ITS to the Distributor. It is fully credited and can be sent over any free-flowing interconnect.
icidtvalid Forward ITS → Distributor

icidtdata[variable:0]a

Forward

icidtkeep[variable:0]a

Forward
icidtlast Forward
icidtdid Forward

Specifies the source ITS.

This signal is only present on the Distributor.

See AXI4-Stream interfaces in Functional integration guidelines of the Arm®CoreLink™ GIC‑600 Generic Interrupt Controller Configuration and Integration Manual for more information.

icidtkeep Forward

Indicates the data bytes that must be transferred.

This signal is only present on the ITS.

icidtwakeup Forward Registered wake signal Indicates that a message is arriving or is about to arrive on the icid bus. Signals icidtvalid and icidtready control data transfer.
icdwtready Reverse Wake Request → Distributor

AXI4-Stream compliant bus for communication from the Distributor to the Wake Request block.

It is fully credited and can be sent over any free-flowing interconnect.

This bus is not exposed when the top level is stitched.

icdwtvalid Forward Distributor → Wake Request
icdwtdata[15:0] Forward
icdwtwakeup Forward

Registered wake signal to indicate that a message is arriving or is about to arrive on the icdw bus. Signals icdwtvalid and icdwtready control data transfer.

This signal is not exposed when the top level is stitched.

icdctready Reverse SPI Collator → Distributor AXI4-Stream compliant bus for communication between the Distributor and the SPI Collator. It is fully credited and must never backpressure. It can be sent over any free-flowing interconnect.
icdctvalid Forward Distributor → SPI Collator
icdctdata[15:0] Forward
icdctlast Forward
icdctwakeup Forward Registered wake signal to indicate that a message is arriving or is about to arrive on the icdc bus. Signals icdctvalid and icdctready control data transfer.
iccdtdest Forward Indicates that the collator number is always 0.
iccdtready Reverse AXI4-Stream compliant bus for communication between the SPI Collator and the Distributor. It is fully credited and must never backpressure. It can be sent over any free-flowing interconnect.
iccdtvalid Forward SPI Collator → Distributor
iccdtdata[15:0] Forward
iccdtlast Forward
iccdtwakeup Forward Registered wake signal to indicate that a message is arriving or is about to arrive on the iccd bus. Signals iccdtvalid and iccdtready control data transfer.
iccdtid Forward

Indicates that the collator number must be tied to 0.

This signal is only present on the Distributor.

a The variable is configuration-dependent.
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